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TMS320DM814X Datasheet(PDF) 340 Page - Texas Instruments |
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TMS320DM814X Datasheet(HTML) 340 Page - Texas Instruments |
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340 / 377 page  TMS320DM8148, TMS320DM8147 SPRS647E – MARCH 2011 – REVISED DECEMBER 2013 www.ti.com 8.17 Peripheral Component Interconnect Express (PCIe) The device supports connections to PCIe-compliant devices via the integrated PCIe master/slave bus interface. The PCIe module is comprised of a dual-mode PCIe core and a SerDes PHY. The device implements a single one-lane PCIe 2.0 (5.0 GT/s) Endpoint/Root Complex port. The device PCIe supports the following features: • Supports Gen1/Gen2 in x1 or x2 mode • One port with one 5 GT/s lane • Single virtual channel (VC), single traffic class (TC) • Single function in end-point mode • Automatic width and speed negotiation and lane reversal • Max payload: 128 byte outbound, 256 byte inbound • Automatic credit management • ECRC generation and checking • Configurable BAR filtering • Supports PCIe messages • Legacy interrupt reception (RC) and generation (EP) • MSI generation and reception • PCI device power management, except D3 cold with vaux • Active state power management state L0 and L1. For more detailed information on the PCIe port peripheral module, see the PCI Express (PCIe) Module chapter of the TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual (Literature Number: SPRUGZ8). The PCIe peripheral on the device conforms to the PCI Express Base 2.0 Specification. 8.17.1 PCIe Peripheral Register Descriptions Table 8-88. PCIe Registers HEX ADDRESS ACRONYM REGISTER NAME 0x5100 0000 PID Peripheral Version and ID 0x5100 0004 CMD_STATUS Command Status 0x5100 0008 CFG_SETUP Config Transaction Setup 0x5100 000C IOBASE IO TLP Base 0x5100 0010 TLPCFG TLP Attribute Configuration 0x5100 0014 RSTCMD Reset Command and Status 0x5100 0020 PMCMD Power Management Command 0x5100 0024 PMCFG Power Management Configuration 0x5100 0028 ACT_STATUS Activity Status 0x5100 0030 OB_SIZE Outbound Size 0x5100 0034 DIAG_CTRL Diagnostic Control 0x5100 0038 ENDIAN Endian Mode 0x5100 003C PRIORITY CBA Transaction Priority 0x5100 0050 IRQ_EOI End of Interrupt 0x5100 0054 MSI_IRQ MSI Interrupt IRQ 0x5100 0064 EP_IRQ_SET Endpoint Interrupt Request Set 0x5100 0068 EP_IRQ_CLR Endpoint Interrupt Request Clear 0x5100 006C EP_IRQ_STATUS Endpoint Interrupt Status 0x5100 0070 GPRO General Purpose 0 340 Peripheral Information and Timings Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320DM8148 TMS320DM8147 |
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