R5F56519FDFP datasheet(114/190 Pages) RENESAS

114 / 190 page

R01DS0276EJ0100 Rev.1.00

Page 114 of 190

Aug 24, 2016

RX65N Group, RX651 Group

5. Electrical Characteristics

Note 1. Supply current values are with all output pins unloaded and all input pull-up MOSs in the off state.

Note 2. Supply of the clock signal to peripheral modules is stopped in this state.

Note 3. ICC depends on f (ICLK) as follows. (ICLK/PCLKA:PCLKB/PCLKC/PCLKD:BCLK:BCLK pin = 10:5:10:5 when EXTAL = 12 MHz)

ICC Max. = 0.31 × f + 6.5 (max. operation in high-speed operating mode)

ICC Typ. = 0.16 × f + 2.8 (ICLK 1 MHz max) (normal operation in high-speed operating mode)

ICC Typ. = 0.4 × f + 1.1 (low-speed operating mode 1)

ICC Max. = 0.15 × f + 6.5 (sleep mode)

Note 4. Whether supply of the clock signal to peripheral modules continues or is stopped only depends on the state determined by the

settings of the bits in module stop control registers A to D.

The setting for the peripheral module clock stopped state is FCLK = BCLK = PCLKA = PCLKB = PCLKC = PCLKD = BCLK pin

= 3.75 MHz (division by 64).

Note 5. The low power consumption function is disabled and DEEPCUT[1:0] = 01b.

Note 6. The low power consumption function is enabled and DEEPCUT[1:0] = 11b.

Note 7. Reference value

Table 5.5

DC Characteristics (3)

Conditions: VCC = AVCC0 = AVCC1 = VREFH0 = VCC_USB = 2.7 to 3.6 V, 2.7

≤ VREFH0 ≤ AVCC0,

VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V,

Ta = Topr

Item

Symbol

Min.

Typ.

Max.

Unit

Test Conditions

Supply

current*1

Max.*2

ICC*3

—

ICLK = 120 MHz

PCLKA = 120 MHz

PCLKB = 60 MHz

PCLKC = 60 MHz

PCLKD = 60 MHz

FCLK = 60 MHz

BCLK = 120 MHz

BCLK pin = 60 MHz

Normal

Peripheral function clock signal

supplied*4

—22

—

Peripheral function clock signal

stopped*4

—12

—

Coremark

Peripheral function clock signal

stopped*4

—15

—

Sleep mode: Supply of the clock signal to peripheral

modules is stopped*4

All-module-clock-stop mode (reference value)

—

Low-speed operating mode 1: Supply of the clock signal

to peripheral modules is stopped*4

—

1.1

—

All clocks 1 MHz

Low-speed operating mode 2: Supply of the clock signal

to peripheral modules is stopped*4

—

1.1

—

All clocks 32.768 kHz

Software standby mode

—

1.6

6.4

Power supplied to standby RAM and USB resume

detecting unit (USB0 only)

—

15.5

μA

Power not

supplied to

standby RAM and

USB resume

detecting unit

(USB0 only)

Power-on reset circuit and low-

power consumption function

disabled*5

—

11.5

Power-on reset circuit and low-

power consumption function

enabled*6

—4.9

Increased by

RTC operation

When a crystal oscillator for low

clock loads is in use

—1

—

When a crystal oscillator for

standard clock loads is in use

—2

—

RTC operating while

VCC is off (with the

battery backup

function, only the RTC

and sub-clock

oscillator operate)

When a crystal oscillator for low

clock loads is in use

—0.9

—

VBATT = 2.0 V,

VCC = 0 V

—1.6

—

VBATT = 3.3 V,

VCC = 0 V

When a crystal oscillator for

standard clock loads is in use

—1.7

—

VBATT = 2.0 V,

VCC = 0 V

—3.3

—

VBATT = 3.3 V,

VCC = 0 V

Inrush current on

returning from deep

software standby mode

Inrush current*7

IRUSH

——

Energy of inrush current*7

ERUSH

——

1.0

μC

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