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R5F56519FDFP Datasheet(PDF) 110 Page - Renesas Technology Corp

Part # R5F56519FDFP
Description  120-MHz, 32-bit RX MCU, on-chip FPU, 240 DMIPS, up to 1-MB flash memory,
PDF  190 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F56519FDFP Datasheet(HTML) 110 Page - Renesas Technology Corp

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R01DS0276EJ0100 Rev.1.00
Page 110 of 190
Aug 24, 2016
RX65N Group, RX651 Group
4. I/O Registers
Note 1. When the same output trigger is specified for pulse output groups 2 and 3 by the PPG0.PCR setting, the PPG0.NDRH address
is 0008 81ECh. When different output
triggers are specified, the PPG0.NDRH addresses for pulse output groups 2 and 3 are 0008 81EEh and 0008 81ECh,
respectively.
Note 2. When the same output trigger is specified for pulse output groups 0 and 1 by the PPG0.PCR setting, the PPG0.NDRL address
is 0008 81EDh. When different output
triggers are specified, the PPG0.NDRL addresses for pulse output groups 0 and 1 are 0008 81EFh and 0008 81EDh,
respectively.
Note 3. When the same output trigger is specified for pulse output groups 6 and 7 by the PPG1.PCR setting, the PPG1.NDRH address
is 0008 81FCh. When different output
triggers are specified, the PPG1.NDRH addresses for pulse output groups 6 and 7 are 0008 81FEh and 0008 81FCh,
respectively.
Note 4. When the same output trigger is specified for pulse output groups 4 and 5 by the PPG1.PCR setting, the PPG1.NDRL address
is 0008 81FDh. When different output
triggers are specified, the PPG1.NDRL addresses for pulse output groups 4 and 5 are 0008 81FFh and 0008 81FDh,
respectively.
Note 5. When the register is accessed while the USB is operating, a delay may be generated in accessing.
Note 6. The address must end with 0h, 4h, 8h, or Ch when access is made in 32-bit units. The address must end with 0h, 2h, 4h, 6h, 8h,
Ah, Ch, or Eh when access is made in 16-bit units.
000D 0152h
RSPI1
RSPI Command Register 1
SPCMD1
16
16
3, 4 PCLKA
1, 2 ICLK
RSPIc
000D 0154h
RSPI1
RSPI Command Register 2
SPCMD2
16
16
3, 4 PCLKA
1, 2 ICLK
RSPIc
000D 0156h
RSPI1
RSPI Command Register 3
SPCMD3
16
16
3, 4 PCLKA
1, 2 ICLK
RSPIc
000D 0158h
RSPI1
RSPI Command Register 4
SPCMD4
16
16
3, 4 PCLKA
1, 2 ICLK
RSPIc
000D 015Ah
RSPI1
RSPI Command Register 5
SPCMD5
16
16
3, 4 PCLKA
1, 2 ICLK
RSPIc
000D 015Ch
RSPI1
RSPI Command Register 6
SPCMD6
16
16
3, 4 PCLKA
1, 2 ICLK
RSPIc
000D 015Eh
RSPI1
RSPI Command Register 7
SPCMD7
16
16
3, 4 PCLKA
1, 2 ICLK
RSPIc
000D 0160h
RSPI1
RSPI Data Control Register 2
SPDCR2
8
8
3, 4 PCLKA
1, 2 ICLK
RSPIc
000D 0300h
RSPI2
RSPI Control Register
SPCR
8
8
3, 4 PCLKA
1, 2 ICLK
RSPIc
000D 0301h
RSPI2
RSPI Slave Select Polarity Register
SSLP
8
8
3, 4 PCLKA
1, 2 ICLK
RSPIc
000D 0302h
RSPI2
RSPI Pin Control Register
SPPCR
8
8
3, 4 PCLKA
1, 2 ICLK
RSPIc
000D 0303h
RSPI2
RSPI Status Register
SPSR
8
8
3, 4 PCLKA
1, 2 ICLK
RSPIc
000D 0304h
RSPI2
RSPI Data Register
SPDR
32
8, 16,
32
3, 4 PCLKA
1, 2 ICLK
RSPIc
000D 0308h
RSPI2
RSPI Sequence Control Register
SPSCR
8
8
3, 4 PCLKA
1, 2 ICLK
RSPIc
000D 0309h
RSPI2
RSPI Sequence Status Register
SPSSR
8
8
3, 4 PCLKA
1, 2 ICLK
RSPIc
000D 030Ah
RSPI2
RSPI Bit Rate Register
SPBR
8
8
3, 4 PCLKA
1, 2 ICLK
RSPIc
000D 030Bh
RSPI2
RSPI Data Control Register
SPDCR
8
8
3, 4 PCLKA
1, 2 ICLK
RSPIc
000D 030Ch
RSPI2
RSPI Clock Delay Register
SPCKD
8
8
3, 4 PCLKA
1, 2 ICLK
RSPIc
000D 030Dh
RSPI2
RSPI Slave Select Negation Delay Register
SSLND
8
8
3, 4 PCLKA
1, 2 ICLK
RSPIc
000D 030Eh
RSPI2
RSPI Next-Access Delay Register
SPND
8
8
3, 4 PCLKA
1, 2 ICLK
RSPIc
000D 030Fh
RSPI2
RSPI Control Register 2
SPCR2
8
8
3, 4 PCLKA
1, 2 ICLK
RSPIc
000D 0310h
RSPI2
RSPI Command Register 0
SPCMD0
16
16
3, 4 PCLKA
1, 2 ICLK
RSPIc
000D 0312h
RSPI2
RSPI Command Register 1
SPCMD1
16
16
3, 4 PCLKA
1, 2 ICLK
RSPIc
000D 0314h
RSPI2
RSPI Command Register 2
SPCMD2
16
16
3, 4 PCLKA
1, 2 ICLK
RSPIc
000D 0316h
RSPI2
RSPI Command Register 3
SPCMD3
16
16
3, 4 PCLKA
1, 2 ICLK
RSPIc
000D 0318h
RSPI2
RSPI Command Register 4
SPCMD4
16
16
3, 4 PCLKA
1, 2 ICLK
RSPIc
000D 031Ah
RSPI2
RSPI Command Register 5
SPCMD5
16
16
3, 4 PCLKA
1, 2 ICLK
RSPIc
000D 031Ch
RSPI2
RSPI Command Register 6
SPCMD6
16
16
3, 4 PCLKA
1, 2 ICLK
RSPIc
000D 031Eh
RSPI2
RSPI Command Register 7
SPCMD7
16
16
3, 4 PCLKA
1, 2 ICLK
RSPIc
000D 0320h
RSPI2
RSPI Data Control Register 2
SPDCR2
8
8
3, 4 PCLKA
1, 2 ICLK
RSPIc
FE7F 7D7Ch
TEMPS
Temperature Sensor Calibration Data Register
TSCDR
32
32
1 to 3 ICLK
TEMPS
FE7F 7D90h
FLASH
Unique ID Register 0
UIDR0
32
32
1 to 3 ICLK
Flash
FE7F 7D94h
FLASH
Unique ID Register 1
UIDR1
32
32
1 to 3 ICLK
Flash
FE7F 7D98h
FLASH
Unique ID Register 2
UIDR2
32
32
1 to 3 ICLK
Flash
FE7F 7D9Ch
FLASH
Unique ID Register 3
UIDR3
32
32
1 to 3 ICLK
Flash
Table 4.1
List of I/O Registers (Address Order) (56 / 56)
Address
Module
Symbol Register Name
Register
Symbol
Number
of Bits
Access
Size
Number of Access Cycles
Related
Function
ICLK
PCLK
ICLK
 PCLK



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