ATM90E32AS-AU-R datasheet(57/84 Pages) ATMEL

57 / 84 page

M90E32AS [DATASHEET]

Atmel-46003B-SE-M90E32AS-Datasheet_02122015

MMode1

PGA Gain Configuration

5.4.2

ENERGY CALIBRATION REGISTERS

PoffsetA

Phase A Active Power offset

Address: 34H

Type: Read/Write

Default Value: 0000H

Bit

Name

Description

15-6

Reserved.

5-0

PGA_GAIN

PGA gain for all ADC channels.

Mapping:

[5:4]: I3

[3:2]: I2

[1:0]: I1

Encoding:

00: 1X (default)

01: 2X

10: 4X

11: N/A

Table-7 Calibration Registers

Address

Read/Write

Type

Functional Description

Power-on Value

Calibration Registers

41H

PoffsetA

R/W

Phase A Active Power Offset

0000H

42H

QoffsetA

R/W

Phase A Reactive Power Offset

0000H

43H

PoffsetB

R/W

Phase B Active Power Offset

0000H

44H

QoffsetB

R/W

Phase B Reactive Power Offset

0000H

45H

PoffsetC

R/W

Phase C Active Power Offset

0000H

46H

QoffsetC

R/W

Phase C Reactive Power Offset

0000H

47H

PQGainA

R/W

Phase A Active/reactive Energy Cali-

bration Gain

0000H

48H

PhiA

R/W

Phase A Calibration Phase Angle

0000H

49H

PQGainB

R/W

Phase B Active/reactive Energy Cali-

bration Gain

0000H

4AH

PhiB

R/W

Phase B Calibration Phase Angle

0000H

4BH

PQGainC

R/W

Phase C Active/reactive Energy Cali-

bration Gain

0000H

4CH

PhiC

R/W

Phase C Calibration Phase Angle

0000H

Address: 41H

Type: Read/Write

Default Value: 0000H

Bit

Name

Description

15-0

offset

Phase A active power offset, signed with complement format.

ATM90E32AS-AU-R Datasheet(PDF) 57 Page - ATMEL Corporation

ATM90E32AS-AU-R Datasheet(HTML) 57 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

Datasheet Download

Link URL