ATM90E32AS-AU-R datasheet(10/84 Pages) ATMEL

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M90E32AS [Datasheet]

Atmel-46003B-SE-M90E32AS-Datasheet_02122015

FUNCTION DESCRIPTION

3.1

POWER SUPPLY

The M90E32AS works with single power rail 3.3V. An on-chip voltage regulator regulates the 1.8V voltage for the digital

logic.

The regulated 1.8V power is connected to the VDD18 pin. It needs to be bypassed by an external capacitor.

The M90E32AS has four power modes: Normal (N mode), Partial Measurement (M mode), Detection (D mode) and Idle (I

mode). In Idle and Detection modes the 1.8V power regulator is not turned on and the digital logic is not powered. When

the logic is not powered, all the configured register values are not kept (all context lost) except for Detection mode related

registers (10H~13H) for Detection mode configuration.

The registers in Partial Measurement mode or Normal mode have to be re-configured when transiting from Idle or Detec-

tion mode. Refer to 3.8 Power Mode for power mode details.

3.2

CLOCK

The M90E32AS has an on-chip oscillator and can directly connect to an external crystal.

The OSCI pin can also be driven with a clock source.

The oscillator will be powered down in Idle and Detection power modes, as described in 3.8 Power Mode.

3.3

RESET

There are three reset sources for the M90E32AS:

RESET pin

On-chip Power On Reset circuit

Software Reset generated by the SoftReset register

3.3.1

RESET PIN

The RESET pin can be asserted to reset the M90E32AS. The RESET pin has RC filter with typical time constant of 2

μs in the

I/O, as well as a 2

μs (typical) de-glitch filter.

Any reset pulse that is shorter than 2

μs can not reset the M90E32AS.

3.3.2

POWER ON RESET (POR)

The POR circuit resets the M90E32AS at power up.

POR circuit triggers reset when:

DVDD power up with crossing the power-up threshold. Refer to Figure-24.

VDD18 regulator changing from disable to enable, i.e. from Idle or Detection mode to Partial Measurement mode or

Normal mode. Refer to Figure-23.

3.3.3

SOFTWARE RESET

Chip reset can be triggered by writing to the SoftReset register in Normal mode. The software reset is the same as the

reset scope generated from the RESET pin or POR.

These three reset sources have the same reset scope.

All digital logics and registers except for some special registers will be subjected to reset.

•

Interface logic: clock dividers

•

Digital core/ logic: All registers except for some special registers. Refer to 5.3.1 Detection Mode Registers.

ATM90E32AS-AU-R Datasheet(PDF) 10 Page - ATMEL Corporation

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