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ADIS16IMU1/PCBZ Datasheet(PDF) 25 Page - Analog Devices |
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ADIS16IMU1/PCBZ Datasheet(HTML) 25 Page - Analog Devices |
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25 / 38 page  Data Sheet ADIS16486 Rev. 0 | Page 25 of 38 Table 117. XA_BIAS_LOW Bit Definition Bits Description (Default = 0x0000) [15:0] X-axis accelerometer offset correction, low word, twos complement, 0 g = 0x0000, 1 LSB = 0.8 mg ÷ 216 = ~0.01221 µg Table 118. XA_BIAS_HIGH Register Definition Page ID Addresses Default Access Flash Backup 0x02 0x1E, 0x1F 0x0000 R/W Yes Table 119. XA_BIAS_HIGH Bit Definition Bits Description (Default = 0x0000) [15:0] X-axis accelerometer offset correction, high word, twos complement, 0 g = 0x0000, 1 LSB = 0.8 mg Calibration, Accelerometer Bias, YA_BIAS_LOW, YA_BIAS_HIGH The YA_BIAS_LOW (see Table 120 and Table 121) and YA_ BIAS_HIGH (see Table 122 and Table 123) registers combine to allow users to adjust the bias of the y-axis accelerometers. The digital format examples in Table 54 also apply to the YA_BIAS_ HIGH register, and the digital format examples in Table 55 apply to the 32-bit number that comes from combining the YA_BIAS_ LOW and YA_BIAS_HIGH registers. These registers influence the y-axis accelerometer measurements in the same manner that the XA_BIAS_LOW and XA_BIAS_HIGH registers influence the x-axis accelerometer measurements (see Figure 26). Table 120. YA_BIAS_LOW Register Definition Page ID Addresses Default Access Flash Backup 0x02 0x20, 0x21 0x0000 R/W Yes Table 121. YA_BIAS_LOW Bit Definition Bits Description (Default = 0x0000) [15:0] Y-axis accelerometer offset correction, low word, twos complement, 0 g = 0x0000, 1 LSB = 0.8 mg ÷ 216 = ~0.01221 µg Table 122. YA_BIAS_HIGH Register Definition Page ID Addresses Default Access Flash Backup 0x02 0x22, 0x23 0x0000 R/W Yes Table 123. YA_BIAS_HIGH Bit Definition Bits Description (Default = 0x0000) [15:0] Y-axis accelerometer offset correction, high word, twos complement, 0 g = 0x0000, 1 LSB = 0.8 mg Calibration, Accelerometer Bias, ZA_BIAS_LOW, ZA_BIAS_HIGH The ZA_BIAS_LOW (see Table 124 and Table 125) and ZA_ BIAS_HIGH (see Table 126 and Table 127) registers combine to allow users to adjust the bias of the z-axis accelerometers. The digital format examples in Table 54 also apply to the ZA_ BIAS_HIGH register, and the digital format examples in Table 55 apply to the 32-bit number that comes from combining the ZA_BIAS_LOW and ZA_BIAS_HIGH registers. These registers influence the z-axis accelerometer measurements in the same manner that the XA_BIAS_LOW and XA_BIAS_HIGH registers influence the x-axis accelerometer measurements (see Figure 26). Table 124. ZA_BIAS_LOW Register Definition Page ID Addresses Default Access Flash Backup 0x02 0x24, 0x25 0x0000 R/W Yes Table 125. ZA_BIAS_LOW Bit Definition Bits Description (Default = 0x0000) [15:0] Z-axis accelerometer offset correction, low word, twos complement, 0 g = 0x0000, 1 LSB = 0.8 mg ÷ 216 = ~0.01221 µg Table 126. ZA_BIAS_HIGH Register Definition Page ID Addresses Default Access Flash Backup 0x02 0x26, 0x27 0x0000 R/W Yes Table 127. ZA_BIAS_HIGH Bit Definition Bits Description (Default = 0x0000) [15:0] Z-axis accelerometer offset correction, high word, twos complement, 0 g = 0x0000, 1 LSB = 0.8 mg Scratch Registers, USER_SCR_x The USER_SCR_1 (see Table 128 and Table 129), USER_SCR_2 (see Table 130 and Table 131), USER_SCR_3 (see Table 132 and Table 133), and USER_SCR_4 (see Table 134 and Table 135) registers provide four locations for users to store information. Table 128. USER_SCR_1 Register Definition Page ID Addresses Default Access Flash Backup 0x02 0x74, 0x75 0x0000 R/W Yes Table 129. USER_SCR_1 Bit Definition Bits Description (Default = 0x0000) [15:0] User defined Table 130. USER_SCR_2 Register Definition Page ID Addresses Default Access Flash Backup 0x02 0x76, 0x77 0x0000 R/W Yes Table 131. USER_SCR_2 Bit Definition Bits Description (Default = 0x0000) [15:0] User defined Table 132. USER_SCR_3 Register Definition Page ID Addresses Default Access Flash Backup 0x02 0x78, 0x79 0x0000 R/W Yes Table 133. USER_SCR_3 Bit Definition Bits Description (Default = 0x0000) [15:0] User defined Table 134. USER_SCR_4 Register Definition Page ID Addresses Default Access Flash Backup 0x02 0x7A, 0x7B 0x0000 R/W Yes Table 135. USER_SCR_4 Bit Definition Bits Description (Default = 0x0000) [15:0] User defined |
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