ADIS16IMU1SLASHPCBZ datasheet(34/38 Pages) AD

34 / 38 page

ADIS16486

Data Sheet

Rev. 0 | Page 34 of 38

FIR FILTERS

The ADIS16486 has four user configurable FIR filter banks. The

sample rate of the FIR filter banks is identical to the IMU

sample rate. Because decimation occurs after the FIR filters, the

FIR sample rate is independent of the decimation rate and not

affected by the setting of the DEC_RATE register. If the user

selects the internally generated sample clock (which is the

default setting), the nominal IMU sample rate (and FIR sample

rate) is 2460 SPS. If the user supplies an external clock by setting

Bit 7 to 1 of the FNCTIO_CRTL register (see Table 142 and

Table 143), the FIR sample rate is the same frequency as the

input synchronization clock provided to the ADIS16486.

The user can individually configure and select one of the four FIR

filter banks for each individual inertial sensor using the FILTR_

BNK_0 (see Table 155) and FILTR_BNK_1 (see Table 157)

registers (see Figure 24). Each FIR filter bank (A, B, C, D) has

120 taps that consume two pages of memory. The coefficient

associated with each tap in each filter bank has its own

dedicated register that uses a 16-bit, twos complement format.

The FIR filter has unity gain when the sum of all of the coefficients

is equal to 32,768. For filter designs that require fewer than 120

taps, write 0x0000 to all unused registers to eliminate the

latency associated with that particular tap.

FIR Filter Bank A, FIR_COEF_A000 to FIR_COEF_A119

Table 201 and Table 202 offer detailed register and bit definitions

for FIR_COEF_A071, one of the FIR coefficient registers in

Bank A (see Table 200).

Table 200. FIR Filter Bank A Memory Map

Page

Page ID

Address

0x05

0x00

PAGE_ID

0x05

0x02 to 0x07

Not used

0x05

0x08

FIR_COEF_A000

0x05

0x0A

FIR_COEF_A001

0x05

0x0C to 0x7C

FIR_COEF_A002 to

FIR_COEF_A058

0x05

0x7E

FIR_COEF_A059

0x06

0x00

PAGE_ID

0x06

0x02 to 0x07

Not used

0x06

0x08

FIR_COEF_A060

0x06

0x0A

FIR_COEF_A061

0x06

0x0C to 0x7C

FIR_COEF_A062 to

FIR_COEF_A118

0x06

0x7E

FIR_COEF_A119

Table 201. FIR_COEF_A071 Register Definition

Page ID

Addresses

Default

Access

Flash Backup

0x06

0x1E, 0x1F

Not applicable

R/W

Yes

Table 202. FIR_COEF_A071 Bit Definition

Bits

Description (No Default)

[15:0]

FIR Bank A, Coefficient 71, twos complement

Use the following sequence to set the FIR_COEF_A071 register

to a decimal value of −169 (0xFF57):

1. Select Page 6 (DIN = 0x8006).

2. Set FIR_COEF_A071, Bits[7:0] = 0x57 (DIN = 0x9E57).

3. Set FIR_COEF_A071, Bits[15:8] = 0xFF (DIN = 0x9FFF).

FIR Filter Bank B, FIR_COEF_B000 to FIR_COEF_B119

Table 203. Filter Bank B Memory Map

Page

Page ID

Address

0x07

0x00

PAGE_ID

0x07

0x02 to

0x07

Not used

0x07

0x08

FIR_COEF_B000

0x07

0x0A

FIR_COEF_B001

0x07

0x0C to

0x7C

FIR_COEF_B002 to

FIR_COEF_B058

0x07

0x7E

FIR_COEF_B059

0x08

0x00

PAGE_ID

0x08

0x02 to

0x07

Not used

0x08

FIR_COEF_B060

0x08

0x0A

FIR_COEF_B061

0x08

0x0C to

0x7C

FIR_COEF_B062 to

FIR_COEF_B118

0x08

0x7E

FIR_COEF_B119

FIR Filter Bank C, FIR_COEF_C000 to FIR_COEF_C119

Table 204. Filter Bank C Memory Map

Page

Page ID

Address

0x09

0x00

PAGE_ID

0x09

0x02 to

0x07

Not used

0x09

0x08

FIR_COEF_C000

0x09

0x0A

FIR_COEF_C001

0x09

0x0C to

0x7C

FIR_COEF_C002 to

FIR_COEF_C058

0x09

0x7E

FIR_COEF_C059

0x0A

0x00

PAGE_ID

0x0A

0x02 to

0x07

Not used

0x0A

0x08

FIR_COEF_C060

0x0A

FIR_COEF_C061

0x0A

0x0C to

0x7C

FIR_COEF_C062 to

FIR_COEF_C118

0x0A

0x7E

FIR_COEF_C119

ADIS16IMU1/PCBZ Datasheet(PDF) 34 Page - Analog Devices

ADIS16IMU1/PCBZ Datasheet(HTML) 34 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

Datasheet Download

Link URL