ADIS16IMU1SLASHPCBZ datasheet(29/38 Pages) AD

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Data Sheet

ADIS16486

Rev. 0 | Page 29 of 38

Continuous Bias Estimation, NULL_CNFG

The NULL_CNFG register (see Table 150 and Table 151) provides

the configuration controls for the CBE, which is associated with

the bias correction update command in GLOB_CMD, Bit 0 (see

Table 141). NULL_CNFG, Bits[3:0] establishes the total average

time (tA) for the bias estimates, and NULL_CNFG, Bits[13:8]

provides on and off controls for each sensor. The factory

default configuration for the NULL_CNFG register enables the

bias null command for the gyroscopes, disables the bias null

command for the accelerometers, and sets the average time to

~26.64 sec. This calculation assumes that the internal sample

clock (fS = 2460 SPS) is used. If the user supplies an external

clock by setting Bit 7 to 1 of the FNCTIO_CRTL register (see

Table 142 and Table 143), fS is the inertial measurement unit

(IMU) sample rate before decimation.

Table 150. NULL_CNFG Register Definition

Page ID

Addresses

Default

Access

Flash Backup

0x03

0x0E, 0x0F

0x070A

R/W

Yes

Table 151. NULL_CNFG Bit Definitions

Bits

Description (Default = 0x070A)

[15:14]

Not used.

Z-axis acceleration bias correction enable (1 = enabled).

Y-axis acceleration bias correction enable (1 = enabled).

X-axis acceleration bias correction enable (1 = enabled).

Z-axis gyroscope bias correction enable (1 = enabled).

Y-axis gyroscope bias correction enable (1 = enabled).

X-axis gyroscope bias correction enable (1 = enabled).

[7:4]

Not used.

[3:0]

Time base control (TBC), range is 0 to 13 (default = 10),

and time base (tB) = 2TBC/fS, where fS is the IMU sample

rate before decimation and is 2460 SPS if the factory

default internal clock is used. The tA required for

autonull = 64 × tB.

When a sensor bit in the NULL_CNFG register is active (equal

to 1), setting GLOB_CMD, Bit 0 = 1 (DIN sequence: 0x8003,

0x8201, 0x8300) causes the corresponding bias correction register

to automatically update with a value that corrects for its present

bias error (from the CBE). For example, setting NULL_CNFG,

Bit 8 = 1 causes an update in the XG_BIAS_LOW (see Table 105)

and XG_BIAS_HIGH (see Table 107) registers.

Power Management, SLP_CNT

The SLP_CNT register (see Table 152 and Table 153) provides

controls for both power-down mode and sleep mode. The trade-

off between power-down mode and sleep mode is idle power

and recovery time. Power-down mode offers the best power

consumption but requires the most time to recover. In addition, all

volatile settings are lost during power-down, whereas sleep

mode preserves these settings.

Table 152. SLP_CNT Register Definition

Page ID

Addresses

Default

Access

Flash Backup

0x03

0x10, 0x11

Not applicable

R/W

Table 153. SLP_CNT Bit Definitions

Bits

Description (No Default)

[15:10]

Not used

Power-down mode

Normal sleep mode

[7:0]

Programmable time bits, 1 sec/LSB, 0x00 = indefinite

To initiate sleep mode for a specific period, select Page 3 (DIN =

0x8003), write the amount of sleep time to SLP_CNT, Bits[7:0],

and set SLP_CNT, Bit 8 = 1 (DIN = 0x9101). Sleep mode begins

when the CS line goes high after setting SLP_CNT, Bit 8 = 1. Use

the following sequence to place the ADIS16486 into sleep mode

for 100 sec:

1. Select Page 3 (DIN = 0x8003).

2. Set SLP_CNT, Bits[7:0] = 0x64 (DIN = 0x9064), 100 sec

sleep time.

3. Set SLP_CNT, Bit 8 = 1 (DIN = 0x9101), start sleep mode.

To initiate an indefinite sleep mode, set SLP_CNT, Bits[7:0] = 0x00

(DIN = 0x9000), and then set SLP_CNT, Bit 8 = 1 (DIN = 0x9101).

To initiate a power-down period of 100 sec, use the sequence

for placing the ADIS16486 into sleep mode for 100 sec with one

exception: set SLP_CNT, Bit 9 = 1 (DIN = 0x9102) instead of

setting SLP_CNT, Bit 8 = 1 (DIN = 0x9101). To initiate an

indefinite power-down, set SLP_CNT, Bits[7:0] = 0x00 first,

and then set SLP_CNT, Bit 9 = 1 (DIN = 0x9102).

To wake the device from sleep or power-down mode, use one of

the following options to restore normal operation:

•

Assert CS from high to low.

•

Pulse RST low, and then high again.

•

Cycle the power.

If the sleep mode and power-down mode bits are both set to

high, the normal sleep mode bit (SLP_CNT, Bit 8) takes

precedence.

FIR Filter Control, FILTR_BNK_0, FILTR_BNK_1

The FILTR_BNK_0 (see Table 154 and Table 155) and FILTR_

BNK_1 (see Table 156 and Table 157) registers provide the

configuration controls for the FIR filter bank in the signal chain

of each sensor (see Figure 24). These registers provide on and

off control for the FIR bank for each inertial sensor, along with

the FIR bank (A, B, C, D) that each sensor uses.

Write commands to the FILTR_BNK_0 and FILTR_BNK_1

registers, which enable or configure the FIR filters and take up

to 101 µs to fully process. During this execution time, the SPI

interface supports normal operation, and the register values

update at the conclusion of the update process.

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