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ADIS16486

Data Sheet

Rev. 0 | Page 10 of 38

THEORY OF OPERATION

INTRODUCTION

The ADIS16486 is an autonomous sensor system that starts up

on its own when it has a valid power supply. After completing its

initialization process, the ADIS16486 begins sampling, processing,

and loading calibrated sensor data into the output registers, which

are accessible using the SPI port. The SPI port typically connects to

a compatible port on an embedded processor (see Figure 9). See

Table 7 for a list of the master processor pin names and functions.

The four SPI signals facilitate synchronous serial data

communication. The factory default configuration provides users

with a data ready signal on the DIO2 pin to trigger consistent

data acquisition (see Figure 28).

SYSTEM

PROCESSOR

SPI MASTER

SCLK

DIN

DOUT

SCLK

MOSI

MISO

+3.3V

IRQ

DIO2

VDD

I/O LINES ARE COMPATIBLE WITH

3.3V LOGIC LEVELS

ADIS16486

Figure 9. Electrical Connection Diagram

Table 7. Generic Master Processor Pin Names and Functions

Mnemonic

Function

Slave select

SCLK

Serial clock

MOSI

Master output, slave input

MISO

Master input, slave output

IRQ

Interrupt request

Table 8 provides a list of settings that describe the SPI protocol of

the ADIS16486. The initialization routine of the master processor

typically establishes these settings using firmware commands to

write them into its serial control registers.

Table 8. Generic Master Processor SPI Settings

Processor Setting

Description

Master

The ADIS16486 operates as a slave

SCLK ≤ 15 MHz

Maximum serial clock rate

SPI Mode 3

CPOL = 1 (polarity), CPHA = 1 (phase)

MSB First Mode

Bit sequence

16-Bit Mode

Shift register and data length

The register structure and SPI port support a simple connection

between the ADIS16486 and an embedded processor platform.

The register structure contains both output data registers and

control registers. The output data registers include the latest

sensor data, an RTC, error flags, alarm flags, and identification

data. The control registers include sample rate, filtering, input

and output, alarms, calibration, and diagnostic configuration

options. All communication between the ADIS16486 and an

external processor involves either reading or writing to one of

the user registers.

TRIAXIAL

GYROSCOPE

TEMPERATURE

SENSOR

TRIAXIAL

ACCELEROMETER

DSP

ADC

OUTPUT

REGISTERS

CONTROL

REGISTERS

CONTROLLER

Figure 10. Basic Operation

The register structure uses a paged addressing scheme that

contains 13 pages, with each page containing 64 register locations.

Each register is 16 bits wide, and each byte has a unique address

within the memory map of that page. The SPI port accesses one

page at a time using the bit sequence in Figure 11. The user

selects the desired page by writing the corresponding page ID to

the PAGE_ID register. Read the PAGE_ID register to

determine which page is currently active. Table 9 displays the

PAGE_ID register contents for each page along with their basic

functions. The PAGE_ID register is located at Address 0x00 on

every page.

Table 9. User Accessible Page Register Assignments

Page

PAGE_ID Value

Function

0x00

Output data, clock, identification

0x01

Reserved

0x02

Calibration

0x03

Control: sample rate, filtering, input

and output, alarms

0x04

Serial number

0x05

FIR Filter Bank A, Coefficient 0 to

Coefficient 59

0x06

FIR Filter Bank A, Coefficient 60 to

Coefficient 119

0x07

FIR Filter Bank B, Coefficient 0 to

Coefficient 59

0x08

FIR Filter Bank B, Coefficient 60 to

Coefficient 119

0x09

FIR Filter Bank C, Coefficient 0 to

Coefficient 59

0x0A

FIR Filter Bank C, Coefficient 60 to

Coefficient 119

0x0B

FIR Filter Bank D, Coefficient 0 to

Coefficient 59

0x0C

FIR Filter Bank D, Coefficient 60 to

Coefficient 119

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