Data Sheet

ADIS16486

Rev. 0 | Page 5 of 38

TIMING SPECIFICATIONS

Table 2.

Parameter

Description

Typ

Max1

Unit

SCLK frequency

0.01

15

MHz

Stall period between data

2

µs

SCLK low period

31

ns

SCLK high period

31

ns

t

CS

CS to SCLK edge

32

ns

DOUT valid after SCLK edge

10

ns

DIN setup time before SCLK rising edge

2

ns

DIN hold time after SCLK rising edge

2

ns

DOUT rise and fall times, ≤100 pF loading

3

8

ns

CS assertion to DOUT active

0

11

ns

SCLK falling edge to DOUT invalid

0

ns

Last SCLK rising edge to CS deassertion

32

ns

CS deassertion to DOUT high impedance

0

9

ns

Data ready pulse width

11

15

µs

Input sync pulse width

5

µs

Input sync to data invalid

560

570

µs

Input sync period

417

µs

1

Guaranteed by design and characterization, but not tested in production.

2

See Table 3 for exceptions to the stall time rating.

Register Write Processing Times

Table 3.

Parameter

Description

Typ

Max

Unit

STALL TIME

FNCTIO_CTRL, Bits[7:4]

Enabling input sync mode

75

µs

Disabling input sync mode

147

µs

FNCTIO_CTRL, Bits[3:0]

Configure data ready

3

µs

FILTR_BNK_0

Enable and/or select finite impulse response (FIR)

filter banks

101

µs

FILTR_BNK_1

Enable and/or select FIR filter banks

101

µs

NULL_CNFG

Configure autonull bias function

116

µs

1

Monitor the data ready signal (see Table 143 for the FNCTIO_CTRL register configuration) for the return of regular pulsing to help minimize system wait times.