ADIS16IMU1SLASHPCBZ datasheet(27/38 Pages) AD

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Data Sheet

ADIS16486

Rev. 0 | Page 27 of 38

When using an external clock, the self test execution times may

vary from the 12 ms listed in Table 1. In addition, false positive

results are possible when executing the ODST while the device

is in motion.

Bias Correction Update

Select Page 3 (DIN = 0x8003) and set GLOB_CMD, Bit 0 = 1

(DIN = 0x8201, then DIN = 0x8300) to update the user offset

registers with the correction factors of the continuous bias

estimator (CBE). Ensure that the inertial platform is stable during

the entire average time for optimal bias estimates.

Auxiliary Input and Output Line Configuration,

FNCTIO_CTRL

The FNCTIO_CTRL register (see Table 142 and Table 143)

provides configuration control for each input and output pin

(DIO1, DIO2, DIO3, and DIO4). Each DIOx pin supports only

one function at a time. In cases where a single pin has two

assignments, the enable bit for the lower priority function

automatically resets to zero (disabling the lower priority function).

The order of priority is as follows, from highest priority to lowest

priority: data ready, sync clock input, alarm indicator, and

general-purpose. Changing the FNCTIO_CTRL, Bits[5:4] bit

settings requires an execution time of 75 ms, whereas changing

the settings of the remaining bits in the FNCTIO_CTRL register

only takes 3 ms. During this execution time (75 ms or 3 ms),

the operational state and the contents of the register remain

unchanged. However, the SPI interface supports normal

communication (for accessing other registers).

Table 142. FNCTIO_CTRL Register Definition

Page ID

Addresses

Default

Access

Flash Backup

0x03

0x06, 0x07

0x000D

R/W

Yes

Table 143. FNCTIO_CTRL Bit Definitions

Bits

Description (Default = 0x000D)

[15:12]

Not used

Alarm indicator: 1 = enabled, 0 = disabled

Alarm indicator polarity: 1 = positive, 0 = negative

[9:8]

Alarm indicator line selection:

00 = DIO1, 01 = DIO2, 10 = DIO3, 11 = DIO4

Sync clock input enable: 1 = enabled, 0 = disabled

Sync clock input polarity:

1 = rising edge, 0 = falling edge

[5:4]

Sync clock input line selection:

00 = DIO1, 01 = DIO2, 10 = DIO3, 11 = DIO4

Data ready enable: 1 = enabled, 0 = disabled

Data ready polarity: 1 = positive, 0 = negative

[1:0]

Data ready line selection:

00 = DIO1, 01 = DIO2, 10 = DIO3, 11 = DIO4

Data Ready Indicator

FNCTIO_CTRL, Bits[3:0] provide three configuration options for

the data ready function: on and off, polarity, and which DIOx

pin is used. The primary purpose of this signal is to drive the

interrupt control line of an embedded processor to synchronize

data collection and minimize latency. The factory default assigns

the DIO2 pin as a positive polarity, data ready signal. This

means that the data in the output registers is valid when the

DIO2 line is high (see Figure 28). This configuration is intended

when the DIO2 pin drives an interrupt service pin that activates

on a low to high pulse.

DIO2

ACTIVE

INACTIVE

Figure 28. Data Ready, when FNCTIO_CTRL, Bits[3:0] = 1101 (Default)

Use the following sequence to change this assignment to the

DIO1 pin with a negative polarity:

1. Select Page 3 (DIN = 0x8003).

2. Set FNCTIO_CTRL, Bits[3:0] = 1000 (DIN = 0x8608, then

DIN = 0x8700).

The period of the data ready signal can vary by up to ±2%.

Input Sync and Clock Control

FNCTIO_CTRL, Bits[7:4] provide configuration options for

using one of the DIOx pins as an input synchronization signal for

sampling inertial sensor data. For example, use the following

sequence to establish the DIO4 pin as a positive polarity, input

clock pin, and to keep the factory default setting for the data ready

function:

1. Select Page 3 (DIN = 0x8003).

2. Set FNCTIO_CTRL, Bits[7:0] = 0xFD (DIN = 0x86FD).

3. Set FNCTIO_CTRL, Bits[15:8] = 0x00 (DIN = 0x8700).

Note that this command also disables the internal sampling

clock. Therefore, data sampling does not occur if an input clock

signal is not present. Use an input clock frequency of 2400 Hz

for the best performance.

Alarm Indicator

FNCTIO_CTRL, Bits[11:8] provide three configuration options

for using one of the DIOx pins as an alarm indicator: on and off,

polarity, and the DIOx pin. The primary purpose of this signal

is to provide an output signal that activates when a bit in the

SYS_E_FLAG register = 1 (see Table 20). For example, use the

following sequence to establish the DIO3 pin as a negative-polarity,

alarm indicator, while preserving the factory default setting for the

data ready function:

1. Select Page 3 (DIN = 0x8003).

2. Set FNCTIO_CTRL, Bits[7:0] = 0x0D (DIN = 0x860D).

3. Set FNCTIO_CTRL, Bits[15:8] = 0x0A (DIN = 0x870A).

General-Purpose Input and Output Control, GPIO_CTRL

Table 144. GPIO_CTRL Register Definition1

Page ID

Addresses

Default

Access

Flash Backup

0x03

0x08, 0x09

0x00X0

R/W

Yes

GPIO_CTRL, Bits[7:4] reflect the logic levels on the DIOx pins and do not have

a default setting.

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