ATO25F1GC-30EC datasheet(17/46 Pages) ETC

17 / 46 page

17/46

Sep.2013. Rev 0.5

1Gbit Serial NAND Flash Memory

FUNCTIONAL DESCRIPTION

7.1

Standard SPI Instructions

The ATO25D1GA is accessed through an SPI compatible bus consisting of four signals: Serial

Clock (CLK). Chip Select (CS#), Serial Data Input (SI) and Serial Data Output (SO). Standard SPI

instructions use the SI input pin to serially write instructions, addresses or data to the device on

the rising edge of CLK. The SO output pin is used to read data or status from the device on the

falling edge of SCLK.

SPI bus operation Modes 0 (0, 0) and 3 (1, 1) are supported. The primary difference between

Mode 0 and Mode 3 concerns the normal state of the SCLK signal when the SPI bus master is in

standby and data is not being transferred to the Serial Flash. For Mode 0 the SCLK signal is

normally low on the falling and rising edges of CS#. For Mode 3 the SCLK signal is normally high

on the falling and rising edges of CS#.

7.2

Quad SPI Instructions

The ATO25D1GA

supports Quad SPI operation when using the “Read from page buffer x4”

command. This instruction allows data to be transferred to or from the device six to seven times

the rate of ordinary Serial Flash. The Quad Read instruction offers a significant improvement in

continuous and random access transfer rates allowing fast code-shadowing to RAM or execution

directly from the SPI bus (XIP). When using Quad SPI instruction the SI and SO pins become

bidirectional SIO0 and SIO1 and the WP# and HOLD# pins become SIO2 and SIO3 respectively.

Quad SPI instructions require the Quad Enable bit (QE) in Status Register to be set.

ATO25F1GC-30EC Datasheet(PDF) 17 Page - List of Unclassifed Manufacturers