ATO25F1GC-30EC datasheet(25/46 Pages) ETC

25 / 46 page

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Sep.2013. Rev 0.5

1Gbit Serial NAND Flash Memory

8.5.4

QE bit

The Quad Enable(QE) need to enable Quad operation. When the QE bit is set to a 0

state(factory default), W# pin and HOLD# are enabled. When the QE bit is set to a 1 the SIO1,

SIO2 and SIO3 pins are enabled.

WARNING : The QE bit should never be set to a 1 during standard SPI operation if the W#

or HOLD# pins are tied directly to the power supply or ground.

8.5.5

P_Fail bit

This bit indicats that a program failure has occurred (P_Fail set to 1). This bit will also be set if

the user attempts to program an invalid address or a locked or protected region, including the

OTP area. This bit is cleared during the PROGRAM EXECUTE command sequence or a

RESET command (P_Fail = 0).

8.5.6

E_Fail bit

This bit indicates that an erase failure has occurred (E_Fail set to 1). This bit will also be set if

the user attempts to erase a locked region, or if the ERASE operation fails. This bit is cleared

(E_Fail = 0) at the start of the BLOCK ERASE command sequence or the RESET command.

Figure 12.

Get Feature Timing

Figure 13.

Set Feature Timing

ATO25F1GC-30EC Datasheet(PDF) 25 Page - List of Unclassifed Manufacturers