ATO25F1GC-30EC datasheet(11/46 Pages) ETC

11 / 46 page

11/46

Sep.2013. Rev 0.5

1Gbit Serial NAND Flash Memory

SPI modes

These devices can be driven by a microcontroller with its SPI peripheral running in either of the

two following modes:



CPOL=0, CPHA=0



CPOL=1, CPHA=1

For these two modes, input data is latched in on the rising edge of Serial Clock (SCLK), and output

data is available from the falling edge of Serial Clock (SCLK).

The difference between the two modes, as shown in Figure 4, is the clock polarity when the bus

master is in Standby mode and not transferring data:



C remains at 0 for (CPOL=0, CPHA=0)



C remains at 1 for (CPOL=1, CPHA=1)

Figure 3.

Bus Master and memory devices on the SPI bus

The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.

Figure 3 shows an example of three devices connected to an MCU, on an SPI bus. Only one

device is selected at a time, so only one device drives the Serial Data Output (SO) line at a time,

the other devices are in the high impedance state. Resistors R (represented in Figure 3) ensure

that the ATO25D1GA is not selected if the Bus Master leaves the CS# line in the high impedance

state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at the

same time (for example, when the Bus Master is reset), the clock line (SCLK) must be connected

to an external pull-down resistor so that, when all inputs/outputs become high impedance, the S

line is pulled High while the SCLK line is pulled Low (thus ensuring that CS# and SCLK do not

become High at the same time, and so, that the tSHCH requirement is met). The typical value of R is

100 kΩ, assuming that the time constant R*C

p (Cp = parasitic capacitance of the bus line) is

shorter than the time during which the Bus Master leaves the SPI bus in high impedance.

Example: Cp = 50 pF, that is R*Cp = 5 µs <=> the application must ensure that the Bus Master

never leaves the SPI bus in the high impedance state for a time period shorter than 5µs.

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