ATO25F1GC-30EC datasheet(19/46 Pages) ETC

19 / 46 page

19/46

Sep.2013. Rev 0.5

1Gbit Serial NAND Flash Memory

Instructions

All instructions, addresses and data are shifted in and out of the device, most significant bit first.

Serial Data Input (SI) is sampled on the first rising edge of Serial Clock (SCLK) after Chip Select

(CS#) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most

significant bit first, on Serial Data input (SI), each bit being latched on the rising edges of Serial

Clock (SCLK).

The instruction set is listed in Table 3.

All attempts to access the memory array during a Write Status Register cycle, Program cycle or

Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase

cycle continues unaffected.

Table 3. Instruction set

Command

Code

Address

Bytes

Dummy

Bytes

Data

Bytes

Note

BLOCK ERASE

D8h

GET FEATURE

0Fh

Refer to Feature Register

SET FEATURE

1Fh

WRITE DISABLE

04h

WRITE ENABLE

06h

PROGRAM LOAD

02h

1 to 2112

PROGRAM LOAD x4

32h

1 to 2112

Command/Address is 1 bit,

data is 4 bit

PROGRAM LOAD

RANDOM DATA

84h

1 to 2112

PROGRAM LOAD

RANDOM DATA x4

34h

1 to 2112

Command/Address is 1 bit,

data is 4 bit

PROGRAM EXECUTE

10h

PAGE READ

13h

READ FROM

PAGE BUFFER

03h,

0Bh

1 to 2112

READ FROM

PAGE BUFFER x4

6Bh

1 to 2112

Command/Address is 1 bit,

data is 4 bit

READ ID

9Fh

Address is 00h to get JEDEC ID

RESET

FFh

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