ATO25F1GC-30EC datasheet(10/46 Pages) ETC

10 / 46 page

10/46

Sep.2013. Rev 0.5

1Gbit Serial NAND Flash Memory

Signal descriptions

2.1

Serial Data output (SO)

– SIO1

This output signal is used to transfer data serially out of the device. Data is shifted out on the

falling edge of Serial Clock (SCLK) at all read mode. Also, When the device is Quad mode, this

pin(SO) is used for SIO1

2.2

Serial Data input (SI)

– SIO0

This input signal is used to transfer data serially into the device. It receives instructions, addresses,

and the data to be programmed. Values are latched on the rising edge of Serial Clock (SCLK).

Also, When the device is Quad mode, this pin(SI) is used for SIO0

2.3

Serial Clock (SCLK)

This input signal provides the timing of the serial interface. Instructions, addresses, or data

present at Serial Data Input (SI) are latched on the rising edge of Serial Clock (SCLK). Data on

Serial Data Output (SO) changes after the falling edge of Serial Clock (SCLK).

2.4

Chip Select (CS#)

When this input signal is High, the device is deselected and Serial Data Output Pins are at high

impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress, the

device will be in the Standby mode (this is not the Deep Power-down mode). Driving Chip Select

(CS#) Low enables the device, placing it in the active power mode.

After Power-up, a falling edge on Chip Select (CS#) is required prior to the start of any instruction.

2.5

Hold (HOLD#)

– SIO3

The Hold (HOLD#) signal is used to pause any serial communications with the device without

deselecting the device.

During the Hold condition, the Serial Data Output (SO) is high impedance, and Serial Data Input

(SI) and Serial Clock (SCLK

) are Don’t Care.

To start the Hold condition, the device must be selected, with Chip Select (CS#) driven Low.

Also, When the QE bit of Status Register is set for

“High”, the Hold# function is not available

and this pin used for SIO3 in Quad mode.

2.6

Write Protect (W#)

– SIO2

The main purpose of this input signal is to freeze the size of the area of memory that is protected

against program or erase instructions (as specified by the values in the BP2, BP1 and BP0 bits of

the Status Register).

Like the Hold# pin, When the QE bit of Status Register is set for

“High”, the W# function is not

available too, and this pin used for SIO2 in Quad mode.

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