NRF9160-SICA-R7 datasheet(161/400 Pages) NORDIC

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Peripherals

tPDM,CLK

CLK

tPDM,s

DIN(R)

DIN (L)

tPDM,h=tPDM,ci

tPDM,s

tPDM,h=tPDM,ci

tPDM,cv

Figure 41: PDM timing diagram

6.10 PWM — Pulse width modulation

The pulse with modulation (PWM) module enables the generation of pulse width modulated signals

on GPIO. The module implements an up or up-and-down counter with four PWM channels that drive

assigned GPIOs.

The following are the main features of a PWM module:

• Programmable PWM frequency

• Up to four PWM channels with individual polarity and duty cycle values

• Edge or center-aligned pulses across PWM channels

• Multiple duty cycle arrays (sequences) defined in RAM

• Autonomous and glitch-free update of duty cycle values directly from memory through EasyDMA (no

CPU involvement)

• Change of polarity, duty cycle, and base frequency possibly on every PWM period

• RAM sequences can be repeated or connected into loops

Decoder

Sequence 0

Sequence 1

Wave Counter

DATA RAM

COMP0

COMP1

COMP2

COMP3

SEQSTARTED[0]

SEQSTARTED[1]

SEQEND[0]

SEQEND[1]

SEQ[n].REFRESH

NEXTSTEP

PSEL.OUT[0]

PSEL.OUT[1]

PSEL.OUT[2]

PSEL.OUT[3]

PWM

Carry/Reload

PRESCALER

PWM_CLK

START

STOP

SEQSTART[0]

SEQSTART[1]

COUNTERTOP

STARTED

STOPPED

Figure 42: PWM module

6.10.1 Wave counter

The wave counter is responsible for generating the pulses at a duty cycle that depends on the compare

values, and at a frequency that depends on COUNTERTOP.

There is one common 15-bit counter with four compare channels. Thus, all four channels will share the

same period (PWM frequency), but can have individual duty cycle and polarity. The polarity is set by a

4418_1315 v2.0

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