NRF9160-SICA-R7 datasheet(162/400 Pages) NORDIC

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Peripherals

value read from RAM (see figure Decoder memory access modes on page 165). Whether the counter

counts up, or up and down, is controlled by the MODE register.

The timer top value is controlled by the COUNTERTOP register. This register value, in conjunction with the

selected PRESCALER of the PWM_CLK, will result in a given PWM period. A COUNTERTOP value smaller

than the compare setting will result in a state where no PWM edges are generated. OUT[n] is held high,

given that the polarity is set to FallingEdge. All compare registers are internal and can only be configured

through decoder presented later. COUNTERTOP can be safely written at any time.

Sampling follows the START task. If DECODER.LOAD=WaveForm, the register value is ignored and taken

from RAM instead (see section Decoder with EasyDMA on page 165 for more details). If DECODER.LOAD

is anything else than the WaveForm, it is sampled following a STARTSEQ[n] task and when loading a new

value from RAM during a sequence playback.

The following figure shows the counter operating in up mode (MODE=PWM_MODE_Up), with three PWM

channels with the same frequency but different duty cycle:

COUNTERTOP

COMP0

COMP1

OUT[0]

OUT[1]

Figure 43: PWM counter in up mode example - FallingEdge polarity

The counter is automatically reset to zero when COUNTERTOP is reached and OUT[n] will invert. OUT[n]

is held low if the compare value is 0 and held high if set to COUNTERTOP, given that the polarity is set to

4418_1315 v2.0

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NRF9160-SICA-R7 Datasheet(PDF) 162 Page - Nordic Semiconductor