NRF9160-SICA-R7 datasheet(185/400 Pages) NORDIC

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Peripherals

2. Desired COUNTER frequency 8 Hz (125 ms counter period)

PRESCALER = round(32.768 kHz / 8 Hz) – 1 = 4095

fRTC = 8 Hz

125 ms counter period

6.11.3 Counter register

The internal <<COUNTER>> register increments on LFCLK when the internal PRESCALER register

(<<PRESC>>) is 0x00. <<PRESC>> is reloaded from the PRESCALER register. If enabled, the TICK event

occurs on each increment of the COUNTER.

PCLK16M

LFCLK

PRESC

<<PRESC>>

0x000

TICK

<<COUNTER>>

0x000002

0x000003

0x000

0x000001

0x000000

Figure 52: Timing diagram - COUNTER_PRESCALER_0

PCLK16M

LFCLK

PRESC

<<PRESC>>

0x001

0x000

0x001

TICK

<<COUNTER>>

0x000001

0x000

0x000000

Figure 53: Timing diagram - COUNTER_PRESCALER_1

6.11.3.1 Reading the counter register

To read the COUNTER register, the internal <<COUNTER>> value is sampled.

To ensure that the <<COUNTER>> is safely sampled (considering that an LFCLK transition may occur during

a read), the CPU and core memory bus are halted for PCLK16M cycles. In addition, the read takes the CPU

two PCLK16M cycles, resulting in the COUNTER register read taking maximum six PCLK16M clock cycles.

6.11.4 Overflow

An OVRFLW event is generated on COUNTER register overflow (overflowing from 0xFFFFFF to 0).

The TRIGOVRFLW task will set the COUNTER value to 0xFFFFF0, to allow software test of the overflow

condition.

Note: The OVRFLW event is disabled by default.

4418_1315 v2.0

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NRF9160-SICA-R7 Datasheet(PDF) 185 Page - Nordic Semiconductor

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