NRF9160-SICA-R7 datasheet(188/400 Pages) NORDIC

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Peripherals

PCLK16M

LFCLK

<<PRESC>>

<<COUNTER>>

CC[0]

COMPARE[0]

0x000

N-1

N+1

N+2

> 62.5 ns

Figure 58: Timing diagram - COMPARE_N+2

If the COUNTER value is N, writing N or N+1 to a CC register may not trigger a COMPARE event.

PCLK16M

LFCLK

<<PRESC>>

<<COUNTER>>

CC[0]

COMPARE[0]

0x000

N-2

N-1

N+1

>= 0 ns

Figure 59: Timing diagram - COMPARE_N+1

If the COUNTER value is N, and the current CC value is N+1 or N+2 when a new CC value is written, a

match may trigger on the previous CC value before the new value takes effect. If the current CC value is

greater than N+2 when the new value is written, there will be no event due to the old value.

PCLK16M

LFCLK

<<PRESC>>

<<COUNTER>>

CC[0]

COMPARE[0]

0x000

N-2

N-1

N+1

>= 0 ns

Figure 60: Timing diagram - COMPARE_N-1

6.11.8 Task and event jitter/delay

Jitter or delay in the RTC, is due to the peripheral clock being a low frequency clock (LFCLK), which is not

synchronous to the faster PCLK16M.

Registers in the peripheral interface that are part of the PCLK16M domain, have a set of mirrored registers

in the LFCLK domain. For example, the COUNTER value accessible from the CPU is in the PCLK16M domain,

and is latched on a read from an internal COUNTER register in the LFCLK domain. The COUNTER register

4418_1315 v2.0

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NRF9160-SICA-R7 Datasheet(PDF) 188 Page - Nordic Semiconductor

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