NRF9160-SICA-R7 datasheet(241/400 Pages) NORDIC

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Peripherals

Mode

Clock polarity

Clock phase

CPOL

CPHA

SPI_MODE0

0 (Active High)

0 (Trailing Edge)

SPI_MODE1

0 (Active High)

1 (Leading Edge)

SPI_MODE2

1 (Active Low)

0 (Trailing Edge)

SPI_MODE3

1 (Active Low)

1 (Leading Edge)

Table 75: SPI modes

6.14.1 Shared resources

The SPI slave shares registers and other resources with other peripherals that have the same ID as the SPI

slave. Therefore, you must disable all peripherals that have the same ID as the SPI slave before the SPI

slave can be configured and used.

Disabling a peripheral that has the same ID as the SPI slave will not reset any of the registers that are

shared with the SPI slave. It is important to configure all relevant SPI slave registers explicitly to secure that

it operates correctly.

The Instantiation table in Instantiation on page 24 shows which peripherals have the same ID as the SPI

slave.

6.14.2 EasyDMA

The SPIS implements EasyDMA for accessing RAM without CPU involvement.

The SPIS peripheral implements the following EasyDMA channels:

Channel

Type

TXD

READER

TXD

RXD

WRITER

RXD

Table 76: SPIS EasyDMA Channels

For detailed information regarding the use of EasyDMA, see EasyDMA on page 45.

If RXD.MAXCNT is larger than TXD.MAXCNT, the remaining transmitted bytes will contain the value defined

in the ORC register.

The END event indicates that EasyDMA has finished accessing the buffer in RAM.

6.14.3 SPI slave operation

SPI slave uses two memory pointers, RXD.PTR and TXD.PTR, that point to the RXD buffer (receive buffer)

and TXD buffer (transmit buffer) respectively. Since these buffers are located in RAM, which can be

accessed by both the SPI slave and the CPU, a hardware based semaphore mechanism is implemented to

enable safe sharing.

Before the CPU can safely update the RXD.PTR and TXD.PTR pointers it must first acquire the SPI

semaphore. The CPU can acquire the semaphore by triggering the ACQUIRE task and then receiving the

ACQUIRED event. When the CPU has updated the RXD.PTR and TXD.PTR pointers the CPU must release the

semaphore before the SPI slave will be able to acquire it.

The CPU releases the semaphore by triggering the RELEASE task, this is illustrated in SPI transaction when

shortcut between END and ACQUIRE is enabled on page 242. Triggering the RELEASE task when the

semaphore is not granted to the CPU will have no effect. See Semaphore operation on page 243 for

more information

4418_1315 v2.0

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