NRF9160-SICA-R7 datasheet(243/400 Pages) NORDIC

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Peripherals

6.14.4 Semaphore operation

The semaphore is a mechanism implemented inside the SPI slave that prevents simultaneous access to the

data buffers by the SPI slave and CPU.

The semaphore is by default assigned to the CPU after the SPI slave is enabled. No ACQUIRED event will be

generated for this initial semaphore handover. An ACQUIRED event will be generated immediately if the

ACQUIRE task is triggered while the semaphore is assigned to the CPU. The figure SPI semaphore FSM on

page 243 illustrates the transitions between states in the semaphore based on the relevant tasks and

events.

RELEASE

FREE

CPU

SPI

CPU PENDING

ACQUIRE

ENABLE change

ACQUIRE

STARTED

STOPPED

ACQUIRE

ACQUIRE &

CSN = high

Figure 77: SPI semaphore FSM

Note: The semaphore mechanism does not, at any time, prevent the CPU from performing read

or write access to the RXD.PTR register, the TXD.PTR registers, or the RAM that these pointers are

pointing to. The semaphore is only telling when these can be updated by the CPU so that safe

sharing is achieved.

The SPI slave will try to acquire the semaphore when STARTED event is detected, the even also indicates

that CSN is currently low. If the SPI slave does not manage to acquire the semaphore at this point (i.e., it

is under CPU's control), the transaction will be ignored. This means that all incoming data on MOSI will

be discarded, and the DEF (default) character will be clocked out on the MISO line throughout the whole

transaction. This will also be the case even if the semaphore is released by the CPU during the transaction.

In case of a race condition where the CPU and the SPI slave try to acquire the semaphore at the same

time, as illustrated in lifeline item 2 in figure SPI transaction when shortcut between END and ACQUIRE is

enabled on page 242, the semaphore will be granted to the CPU.

If the SPI slave acquires the semaphore, the transaction will be granted. The incoming data on MOSI will

be stored in the RXD buffer and the data in the TXD buffer will be clocked out on MISO.

When a granted transaction is completed and CSN goes high, the SPI slave will automatically release the

semaphore and generate the END event.

As long as the semaphore is available, the SPI slave can be granted multiple transactions one after the

other.

If the CPU tries to acquire the semaphore while it is assigned to the SPI slave, an immediate handover

will not be granted. However, the semaphore will be handed over to the CPU as soon as the SPI slave

has released the semaphore after the granted transaction is completed. If the END_ACQUIRE shortcut

is enabled and the CPU has triggered the ACQUIRE task during a granted transaction, only one ACQUIRE

request will be served following the END event.

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