NRF9160-SICA-R7 datasheet(259/400 Pages) NORDIC

259 / 400 page

Peripherals

6.15 SPU — System protection unit

SPU is the central point in the system to control access to memories, peripherals and other resources.

Listed here are the main features of the SPU:

• ARM TrustZone support, allowing definition of secure, non-secure and non-secure callable memory

regions

• Extended ARMTrustZone, protecting memory regions and peripherals from non-CPU devices like

EasyDMA transfer

• Pin access protection, preventing non-secure code and peripherals from accessing secure pin resources

• DPPI access protection, realized by preventing non-secure code and peripherals to publish from or

subscribe to secured DPPI channels

• External domain access protection, controlling access rights from other MCUs

6.15.1 General concepts

SPU provides a register interface to control the various internal logic blocks that monitor access to

memory-mapped slave devices (RAM, flash, peripherals, etc) and other resources (device pins, DPPI

channels, etc).

For memory-mapped devices like RAM, flash and peripherals, the internal logic checks the address and

attributes (e.g. read, write, execute, secure) of the incoming transfer to block it if necessary. Whether a

secure resource can be accessed by a given master is defined:

For a CPU-type master

By the security state of the CPU and the security state reported by the SPU, for the address in the bus

transfer

For a non-CPU master

By the security attribute of the master that initiates the transfer, defined by a SPU register

The Simplified view of the protection of RAM, flash and peripherals using SPU on page 259 shows a

simplified view of the SPU registers controlling several internal modules.

RAM

Blocks

RAM

Blocks

Cortex-M33

TrustZone-M

aware

CPU

Implementation

defined

attribution unit

(IDAU)

Other

bus

masters

Bus

interconnect

Secure control

logic

Peripherals

RAM

blocks

Flash

SPU

configuration

registers

Secure

control

logic

Internal system logic

Figure 80: Simplified view of the protection of RAM, flash and peripherals using SPU

The protection logic implements a read-as-zero/write-ignore (RAZ/WI) policy:

4418_1315 v2.0

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