NRF9160-SICA-R7 datasheet(260/400 Pages) NORDIC

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Peripherals

• A blocked read operation will always return a zero value on the bus, preventing information leak

• A write operation to a forbidden region or peripheral will be ignored

An error is reported through dedicated error signals. For security state violations from an M33 master

this will be a SecureFault exception, for other violations this will be an SPU event. The SPU event can be

configured to generate an interrupt towards the CPU.

Other resources like pins and DPPI channels are protected by comparing the security attributes of the

protected resource with the security attribute of the peripheral that wants to access it. The SPU is the only

place where those security attributes can be configured.

6.15.1.1 Special considerations for ARM TrustZone for Cortex-M enabled system

For a ARM TrustZone for Cortex-M enabled CPU, the SPU also controls custom logic.

Custom logic is shown as the implementation defined attribution unit (IDAU) in figure Simplified view of

the protection of RAM, flash and peripherals using SPU on page 259. Full support is provided for:

• ARM TrustZone for Cortex-M related instructions, like test target (TT) for reporting the security

attributes of a region

• Non-secure callable (NSC) regions, to implement secure entry points from non-secure code

The SPU provides the necessary registers to configure the security attributes for memory regions and

peripherals. However, as a requirement to use the SPU, the secure attribution unit (SAU) needs to be

disabled and all memory set as non-secure in the ARM core. This will allow the SPU to control the IDAU

and set the security attribution of all addresses as originally intended.

6.15.2 Flash access control

The flash memory space is divided in regions, each of them with configurable permissions settings.

The flash memory space is divided into 32 regions of 32 KiB .

For each region, four different types of permissions can be configured:

Read

Allows data read access to the region. Note that code fetch from this region is not controlled by the

read permission but by the execute permission described below.

Write

Allows write or page erase access to the region

Execute

Allows code fetch from this region, even if data read is disabled

Secure

Allows only bus accesses with the security attribute set to access the region

Permissions can be set independently. For example, it is possible to configure a flash region to be

accessible only through secure transfer, being read-only (no write allowed) and non-executable

(no code fetch allowed). For each region, permissions can be set and then locked by using the

FLASHREGION[n].PERM.LOCK bit, to prevent subsequent modifications.

Note that the debugger is able to step through execute-protected memory regions.

The following figure shows the flash memory space and the divided regions:

4418_1315 v2.0

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NRF9160-SICA-R7 Datasheet(PDF) 260 Page - Nordic Semiconductor