NRF9160-SICA-R7 datasheet(314/400 Pages) NORDIC

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Peripherals

6.18.3 TWI slave responding to a read command

Before the TWI slave can respond to a read command, the TWI slave must be configured correctly and

enabled via the ENABLE register. When enabled, the TWI slave will be in its IDLE state. .

A read command is started when the TWI master generates a start condition on the TWI bus, followed

by clocking out the address and the READ/WRITE bit set to 1 (WRITE=0, READ=1). The READ/WRITE bit is

followed by an ACK/NACK bit (ACK=0 or NACK=1) response from the TWI slave.

The TWI slave is able to listen for up to two addresses at the same time. This is configured in the ADDRESS

registers and the CONFIG register.

The TWI slave will only acknowledge (ACK) the read command if the address presented by the master

matches one of the addresses the slave is configured to listen for. The TWI slave will generate a READ

event when it acknowledges the read command.

The TWI slave is only able to detect a read command from the IDLE state.

The TWI slave will set an internal 'TX prepared' flag when the PREPARETX task is triggered.

When the read command is received, the TWI slave will enter the TX state if the internal 'TX prepared' flag

is set.

If the internal 'TX prepared' flag is not set when the read command is received, the TWI slave will stretch

the master's clock until the PREPARETX task is triggered and the internal 'TX prepared' flag is set.

The TWI slave will generate the TXSTARTED event and clear the 'TX prepared' flag ('unprepare TX') when it

enters the TX state. In this state the TWI slave will send the data bytes found in the transmit buffer to the

master using the master's clock.

The TWI slave will go back to the IDLE state if the TWI slave receives a restart command when it is in the

TX state.

The TWI slave is stopped when it receives the stop condition from the TWI master. A STOPPED event

will be generated when the transaction has stopped. The TWI slave will clear the 'TX prepared' flag

('unprepare TX') and go back to the IDLE state when it has stopped.

The transmit buffer is located in RAM at the address specified in the TXD.PTR register. The TWI slave will

only be able to send TXD.MAXCNT bytes from the transmit buffer for each transaction. If the TWI master

forces the slave to send more than TXD.MAXCNT bytes, the slave will send the byte specified in the ORC

The EasyDMA configuration registers, see TXD.PTR etc., are latched when the TXSTARTED event is

generated.

The TWI slave can be forced to stop by triggering the STOP task. A STOPPED event will be generated when

the TWI slave has stopped. The TWI slave will clear the 'TX prepared' flag and go back to the IDLE state

when it has stopped, see also Terminating an ongoing TWI transaction on page 317.

Each byte sent from the slave will be followed by an ACK/NACK bit sent from the master. The TWI master

will generate a NACK following the last byte that it wants to receive to tell the slave to release the bus so

that the TWI master can generate the stop condition. The TXD.AMOUNT register can be queried after a

transaction to see how many bytes were sent.

A typical TWI slave read command response is shown in the following figure. Occurrence 2 in the figure

illustrates clock stretching performed by the TWI slave following a SUSPEND task.

4418_1315 v2.0

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