NRF9160-SICA-R7 datasheet(315/400 Pages) NORDIC

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Peripherals

ADDR

N-1

Stretch

Figure 100: The TWI slave responding to a read command

6.18.4 TWI slave responding to a write command

Before the TWI slave can respond to a write command, the TWI slave must be configured correctly and

enabled via the ENABLE register. When enabled, the TWI slave will be in its IDLE state.

A write command is started when the TWI master generates a start condition on the TWI bus, followed

by clocking out the address and the READ/WRITE bit set to 0 (WRITE=0, READ=1). The READ/WRITE bit is

followed by an ACK/NACK bit (ACK=0 or NACK=1) response from the slave.

The TWI slave is able to listen for up to two addresses at the same time. This is configured in the ADDRESS

registers and the CONFIG register.

The TWI slave will only acknowledge (ACK) the write command if the address presented by the master

matches one of the addresses the slave is configured to listen for. The TWI slave will generate a WRITE

event if it acknowledges the write command.

The TWI slave is only able to detect a write command from the IDLE state.

The TWI slave will set an internal 'RX prepared' flag when the PREPARERX task is triggered.

When the write command is received, the TWI slave will enter the RX state if the internal 'RX prepared'

flag is set.

If the internal 'RX prepared' flag is not set when the write command is received, the TWI slave will stretch

the master's clock until the PREPARERX task is triggered and the internal 'RX prepared' flag is set.

The TWI slave will generate the RXSTARTED event and clear the internal 'RX prepared' flag ('unprepare RX')

when it enters the RX state. In this state, the TWI slave will be able to receive the bytes sent by the TWI

master.

The TWI slave will go back to the IDLE state if the TWI slave receives a restart command when it is in the

RX state.

The TWI slave is stopped when it receives the stop condition from the TWI master. A STOPPED event will

be generated when the transaction has stopped. The TWI slave will clear the internal 'RX prepared' flag

('unprepare RX') and go back to the IDLE state when it has stopped.

The receive buffer is located in RAM at the address specified in the RXD.PTR register. The TWI slave will

only be able to receive as many bytes as specified in the RXD.MAXCNT register. If the TWI master tries to

send more bytes to the slave than it can receive, the extra bytes are discarded and NACKed by the slave. If

this happens, an ERROR event will be generated.

The EasyDMA configuration registers, see RXD.PTR etc., are latched when the RXSTARTED event is

generated.

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NRF9160-SICA-R7 Datasheet(PDF) 315 Page - Nordic Semiconductor