NRF9160-SICA-R7 datasheet(317/400 Pages) NORDIC

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Peripherals

6.18.6 Terminating an ongoing TWI transaction

In some situations, e.g. if the external TWI master is not responding correctly, it may be required to

terminate an ongoing transaction.

This can be achieved by triggering the STOP task. In this situation, a STOPPED event will be generated

when the TWI has stopped independent of whether or not a STOP condition has been generated on the

TWI bus. The TWI slave will release the bus when it has stopped and go back to its IDLE state.

6.18.7 Low power

When putting the system in low power and the peripheral is not needed, lowest possible power

consumption is achieved by stopping, and then disabling the peripheral.

The STOP task may not be always needed (the peripheral might already be stopped), but if it is sent,

software shall wait until the STOPPED event was received as a response before disabling the peripheral

through the ENABLE register.

6.18.8 Slave mode pin configuration

The SCL and SDA signals associated with the TWI slave are mapped to physical pins according to the

configuration specified in the PSEL.SCL and PSEL.SDA registers respectively.

The PSEL.SCL and PSEL.SDA registers and their configurations are only used as long as the TWI slave is

enabled, and retained only as long as the device is in ON mode. When the peripheral is disabled, the pins

will behave as regular GPIOs, and use the configuration in their respective OUT bit field and PIN_CNF[n]

To secure correct signal levels on the pins used by the TWI slave when the system is in OFF mode, and

when the TWI slave is disabled, these pins must be configured in the GPIO peripheral as described in the

following table.

Only one peripheral can be assigned to drive a particular GPIO pin at a time. Failing to do so may result in

unpredictable behavior.

TWI slave signal

TWI slave pin

Direction

Output value

Drive strength

SCL

As specified in PSEL.SCL

Input

Not applicable

S0D1

SDA

As specified in PSEL.SDA

Input

Not applicable

S0D1

Table 95: GPIO configuration before enabling peripheral

6.18.9 Registers

Base address Peripheral

Instance

Secure mapping

DMA security

Description

Configuration

0x50008000

0x40008000

TWIS

TWIS0 : S

TWIS0 : NS

Two-wire interface slave 0

0x50009000

0x40009000

TWIS

TWIS1 : S

TWIS1 : NS

Two-wire interface slave 1

0x5000A000

0x4000A000

TWIS

TWIS2 : S

TWIS2 : NS

Two-wire interface slave 2

0x5000B000

0x4000B000

TWIS

TWIS3 : S

TWIS3 : NS

Two-wire interface slave 3

Table 96: Instances

Offset

Security Description

TASKS_STOP

0x014

Stop TWI transaction

4418_1315 v2.0

317

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