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HC705RC17GRS/D Datasheet(PDF) 53 Page - NXP Semiconductors |
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HC705RC17GRS/D Datasheet(HTML) 53 Page - NXP Semiconductors |
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53 / 126 page  Low-Power Modes Wait Mode MC68HC705RC17 — Rev. 2.0 General Release Specification Low-Power Modes During wait mode, the I bit in the CCR is cleared to enable interrupts. All other registers, memory, and input/output lines remain in their previous states. The timer may be enabled to allow a periodic exit from wait mode. NOTE: For minimum current consumption, the phase-locked loop (PLL) should be disabled or turned off before entering wait mode. Figure 6-2. Stop/Wait Flowchart TURN ON OSCILLATOR. WAIT FOR TIME DELAY TO STABILIZE. 1. FETCH RESET VECTOR OR 2. SERVICE INTERRUPT A. STACK B. SET I BIT C. VECTOR TO INTERRUPT ROUTINE RESTART PROCESSOR CLOCK. 1. FETCH RESET VECTOR OR 2. SERVICE INTERRUPT A. STACK B. SET I BIT C. VECTOR TO INTERRUPT ROUTINE Y Y Y Y Y N N N N N STOP WAIT OSCILLATOR ACTIVE. CORE TIMER CLOCK ACTIVE. PROCESSOR CLOCKS STOPPED. STOP OSCILLATOR AND ALL CLOCKS. CLEAR I BIT. IR TIMER INTERNAL INTERRUPT? CORE TIMER INTERNAL INTERRUPT? N Y Y IR TIMER CLOCK ACTIVE. EXTERNAL INTERRUPT (IRQ)? (PTB KEYSCAN PULLUPS) EXTERNAL (IRQ)? (PTB KEYSCAN PULLUPS) INTERRUPT LPRST OR RESET? LPRST OR RESET? Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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