HC705RC17GRSSLASHD datasheet(56/126 Pages) NXP

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Parallel Input/Output (I/O)

General Release Specification

MC68HC705RC17 — Rev. 2.0

Parallel Input/Output (I/O)

7.3 Port A

Port A is an 8-bit bidirectional port which does not share any of its pins

with other subsystems. The port A data register is at $0000 and the data

direction register (DDR) is at $0004. Reset does not affect the data

to inputs. Writing a 1 to a DDR bit sets the corresponding port bit to

output mode.

7.4 Port B

Port B is an 8-bit bidirectional port which does not share any of its pins

with other subsystems. The address of the port B data register is $0001

and the data direction register (DDR) is at address $0005. Reset does

not affect the data register, but clears the data direction register, thereby

returning the ports to inputs. Writing a 1 to a DDR bit sets the

corresponding port bit to output mode. Each of the port B pins has a

mask programmable pullup device that can be enabled. When the pullup

device is enabled, this pin will also become an interrupt pin. The edge or

edge and level sensitivity of the IRQ pin will also pertain to the enabled

port B pins. Care needs to be taken when using port B pins that have the

pullup enabled. Before switching from an output to an input, the data

should be preconditioned to a logic 1 or the I bit should be set in the

condition code register to prevent an interrupt from occurring.

NOTE:

When a port B pin is configured as an output, its corresponding keyscan

interrupt is disabled, regardless of its mask option.

Figure 7-1. Port B Pullup Option

PB7

VDD

DDR BIT

NORMAL PORT CIRCUITRY

AS SHOWN IN FIGURE 7-2

IRQ

TO INTERRUPT

LOGIC

MASK OPTION (PB7PU)

DISABLED

ENABLED

FROM ALL OTHER PORT B PINS

IRQEN

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705RC17GRS/D Datasheet(PDF) 56 Page - NXP Semiconductors

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