HC705RC17GRSSLASHD datasheet(119/126 Pages) NXP

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Electrical Specifications

DC Electrical Characteristics (3.3 Vdc)

MC68HC705RC17 — Rev. 2.0

General Release Specification

Electrical Specifications

13.7 DC Electrical Characteristics (3.3 Vdc)

Characteristic

Symbol

Min

Typ

Max

Unit

Output Voltage

ILoad = 10.0 µA

ILoad = –10.0 µA

VOL

VOH

—

VDD –0.1

—

0.1

—

Output High Voltage

(ILoad –1.6 mA) Port A, Port B, Port C (1–7)

(ILoad –10 mA) IRO

(ILoad –1.2 mA) Port C (Bit 0)

VOH

VDD –0.3

VDD –0.7

VDD –0.3

VDD –0.1

—

Output Low Voltage

(ILoad = 1.0 mA) Port A, Port B, Port C (1–7)

(ILoad = 8.0 mA) IRO

(ILoad = 7.0 mA) Port C (Bit 0)

VOL

—

0.1

0.3

0.8

0.3

Input High Voltage

Port A, Port B, Port C, IRQ, RESET, LPRST, OSC1

VIH

0.7 x VDD

—VDD

Input Low Voltage

Port A, Port B, Port C, IRQ, RESET, LPRST, OSC1

VIL

VSS

—

0.3 x VDD

EPROM Programming Voltage

VPP

14.5

—

15.5

Supply Current (see Notes)

Run (fOP = 2.1 MHz)

Wait with PLL Enabled (fOP = 2.1 MHz)

Wait with PLL Disabled (fOP = 16.384 kHz)

Stop

25 oC

0 oC to +70 oC

IDD

—

TBD

0.15

TBD

4.0

8.0

µA

I/O Ports Hi-Z Leakage Current

Port A, Port B, Port C

IOZ

–6

—

µA

Input Current

RESET, LPRST, IRQ, OSC1

PB0–PB7 with Pullups Enabled (VIN = 0.3 x VDD)

PB0–PB7 with Pullups Enabled (VIN = 0.7 x VDD)

IIn

–0.6

–25

–15

—

–80

–50

0.6

–105

–65

µA

Capacitance

Ports (as Input or Output)

RESET, LPRST, IRQ

COut

CINT

—

NOTES:

VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = 0 °C to +70 °C, unless otherwise noted

All values shown reflect average measurements.

Typical values at midpoint of voltage range, 25 oC only

All current measurements represent the summation of current through VDD and VDDSYN supply pins.

To minimize current consumption in wait mode, disable the PLL before executing the WAIT instruction. Internal bus

speed will be that of the 32.768-kHz external frequency.

Wait IDD: only core timer active

Run (with PLL enabled) IDD, wait IDD (with PLL enabled): Measured using external square wave clock source

OSC = 4.2 MHz); all inputs 0.2 V from rail; no dc loads;; less than 50 pF on all outputs; C

L = 20 pF on OSC2. Wait

IDD (with PLL disabled): Measured using external square wave clock source (fosc = 33 kHz).

Wait, stop IDD: Port A and port C configured as inputs, port B configured as outputs; VIL = 0.2 V; VIH = VDD –0.2 V

Stop IDD is measured with OSC1 = VSS.

10. Wait IDD is affected linearly by the OSC2 capacitance.

11. Pullups are designed to be capable of pulling to VIH within 10 µs for a 100 pF, 4-kΩ load.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705RC17GRS/D Datasheet(PDF) 119 Page - NXP Semiconductors

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