 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
HC705V8GRS/D Datasheet(PDF) 156 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
HC705V8GRS/D Datasheet(HTML) 156 Page - NXP Semiconductors |
|
|
156 / 172 page  SECTION 17: ELECTRICAL SPECIFICATIONS Page 145 MC68HC705V8 Specification Rev. 2.1 NOTES: 1. All values shown reflect average measurements. 2. Typical values at midpoint of voltage range, 25 °C only. 3. Run (Operating) IDD, Wait IDD: Measured using external square wave clock source to OSC1 (fOSC = 4.2 MHz), all inputs 0.2 Vdc from rail; no DC loads, less than 50 pF on all outputs, CL = 20 pF on OSC2. 4. Wait, Stop IDD: All ports configured as inputs, VIL = 0.2 Vdc, VIH = VDD-0.2 Vdc. 5. Stop IDD measured with OSC1 = VSS. 6. Wait IDD is affected linearly by the OSC2 capacitance. 7. Total. * Not Tested. VDD slew rate rising * 0.1 — S VDDR V/ µs — VDD slew rate falling* 0.05 — S VDDF V/ µs — POR Reset Voltage * 100 — V POR mV — Low Voltage Reset Inhibit 4.2 — V LVRI V 3.5 Low Voltage Reset Recover 4.5 — V LVRR V 3.6 Low Voltage Reset Inhibit/Recover Hysteresis 0.3 0.2 H LVR V 0.1 Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
New Zealand ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
