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HC705CT4GRS/D Datasheet(PDF) 48 Page - NXP Semiconductors

Part # HC705CT4GRS/D
Description  General Release Specification
PDF  152 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

HC705CT4GRS/D Datasheet(HTML) 48 Page - NXP Semiconductors

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Resets
General Release Specification
MC68HC705CT4 — Rev. 2.0
48
Resets
MOTOROLA
5.4.2.5 COP Register
The COP register is shared with the MSB of an unimplemented user
interrupt vector as shown in Figure 5-3. Reading this location returns
whatever user data has been programmed at this location. Writing a zero
to the COPR bit in this location clears the COP watchdog timer.
5.4.3 Illegal Address
An illegal address reset is generated when the CPU attempts to fetch an
instruction from either unimplemented address space ($0130 to $0AFF)
or I/O address space ($0000 to $002F).
Table 5-1. COP Watchdog Timer Recommendations
IF the following conditions exist:
THEN the COP Watchdog Timer should be:
WAIT Time
WAIT Time less than COP Timeout
Enable or Disable COP by Mask Option
WAIT Time More than COP Timeout
Disable COP by Mask Option
Any length WAIT Time
Disable COP by Mask Option
Addr
Register Name
Bit 7
654321
Bit 0
$1FF0
Unimplemented Vector
and COP Watchdog Timer
Read:
XXXXXXXX
Write:
COPR
= Unimplemented
Figure 5-3. COP Watchdog Timer Location
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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