HC705CT4GRSSLASHD datasheet(88/152 Pages) NXP

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Dual Phase-Locked Loop (PLL)

General Release Specification

MC68HC705CT4 — Rev. 2.0

Dual Phase-Locked Loop (PLL)

MOTOROLA

TXON — TX Counter Enable

When set, this bit enables the PLL transmit counter.

When clear, it stops the counter in a reset state to save power. TXON

also shuts off the associated phase detector and holds it in three-

state. Initializing the transmit counter before it is enabled is

recommended.

REFON — Reference Counter Enable

When set, this bit enables the PLL reference counter.

When clear, REFON stops the reference counter in a reset state to

save power. Initializing the reference counter before it is enabled is

recommended.

RLOCK — Receive Lock Detect

This bit is read only and is not latched. When set, this bit is a real-time

indication of an active correction pulse from the phase detect in

progress. When clear, no correction is made and the output from the

phase detect is three-stated. Using multiple reads at known intervals

will allow the user to filter and judge a LOCK condition.

TLOCK — Transmit Lock Detect

This bit is read only and is not latched.When set, this bit is a real-time

indication of an active correction pulse from the phase detect in

progress. When clear, no correction is made and the output from the

phase detect is three-stated. Using multiple reads at known intervals

will allow the user to filter and judge a LOCK condition.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705CT4GRS/D Datasheet(PDF) 88 Page - NXP Semiconductors