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MC908QT4MPE Datasheet(PDF) 138 Page - Freescale Semiconductor, Inc |
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MC908QT4MPE Datasheet(HTML) 138 Page - Freescale Semiconductor, Inc |
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138 / 184 page ![]() Development Support MC68HC908QY/QT Family Data Sheet, Rev. 5 138 Freescale Semiconductor 15.2.2.5 Break Flag Control Register The break control register (BFCR) contains a bit that enables software to clear status bits while the MCU is in a break state. BCFE — Break Clear Flag Enable Bit This read/write bit enables software to clear status bits by accessing status registers while the MCU is in a break state. To clear status bits during the break state, the BCFE bit must be set. 1 = Status bits clearable during break 0 = Status bits not clearable during break 15.2.3 Low-Power Modes The WAIT and STOP instructions put the MCU in low power- consumption standby modes. If enabled, the break module will remain enabled in wait and stop modes. However, since the internal address bus does not increment in these modes, a break interrupt will never be triggered. 15.3 Monitor Module (MON) This subsection describes the monitor module (MON) and the monitor mode entry methods. The monitor allows debugging and programming of the microcontroller unit (MCU) through a single-wire interface with a host computer. Monitor mode entry can be achieved without use of the higher test voltage, VTST, as long as vector addresses $FFFE and $FFFF are blank, thus reducing the hardware requirements for in-circuit programming. Features include: • Normal user-mode pin functionality on most pins • One pin dedicated to serial communication between MCU and host computer • Standard non-return-to-zero (NRZ) communication with host computer • Execution of code in random-access memory (RAM) or FLASH • FLASH memory security feature(1) • FLASH memory programming interface • Use of external 9.8304 MHz oscillator to generate internal frequency of 2.4576 MHz • Simple internal oscillator mode of operation (no external clock or high voltage) • Monitor mode entry without high voltage, VTST, if reset vector is blank ($FFFE and $FFFF contain $FF) • Standard monitor mode entry if high voltage is applied to IRQ Address: $FE03 Bit 7 654321 Bit 0 Read: BCFE RRRRRRR Write: Reset: 0 R = Reserved Figure 15-8. Break Flag Control Register (BFCR) 1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or copying the FLASH difficult for unauthorized users. |
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