MC908QT4MPE datasheet(137/184 Pages) FREESCALE

137 / 184 page

Break Module (BRK)

MC68HC908QY/QT Family Data Sheet, Rev. 5

Freescale Semiconductor

137

15.2.2.3 Break Auxiliary Register

The break auxiliary register (BRKAR) contains a bit that enables software to disable the COP while the

MCU is in a state of break interrupt with monitor mode.

BDCOP — Break Disable COP Bit

This read/write bit disables the COP during a break interrupt. Reset clears the BDCOP bit.

1 = COP disabled during break interrupt

0 = COP enabled during break interrupt

15.2.2.4 Break Status Register

The break status register (BSR) contains a flag to indicate that a break caused an exit from wait mode.

This register is only used in emulation mode.

SBSW — SIM Break Stop/Wait

SBSW can be read within the break state SWI routine. The user can modify the return address on the

stack by subtracting one from it.

1 = Wait mode was exited by break interrupt

0 = Wait mode was not exited by break interrupt

Address: $FE02

Bit 7

654321

Bit 0

Read:

0000000

BDCOP

Write:

Reset:

00000000

= Unimplemented

Figure 15-6. Break Auxiliary Register (BRKAR)

Address: $FE00

Bit 7

654321

Bit 0

Read:

RRRRRR

SBSW

Write:

Note(1)

Reset:

= Reserved

1. Writing a 0 clears SBSW.

Figure 15-7. Break Status Register (BSR)

MC908QT4MPE Datasheet(PDF) 137 Page - Freescale Semiconductor, Inc

MC908QT4MPE Datasheet(HTML) 137 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL