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MSP430F14X Datasheet(PDF) 33 Page - Texas Instruments

Part # MSP430F14X
Description  MSP430F14x, MSP430F14x1, MSP430F13x Mixed-Signal Microcontrollers
PDF  83 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

MSP430F14X Datasheet(HTML) 33 Page - Texas Instruments

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Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
SR/CG1/R2
Constant Generator
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R15
General-Purpose Register
R14
33
MSP430F149, MSP430F148, MSP430F147
MSP430F1491, MSP430F1481, MSP430F1471
MSP430F135, MSP430F133
www.ti.com
SLAS272H – JULY 2000 – REVISED MAY 2018
Submit Documentation Feedback
Product Folder Links: MSP430F149 MSP430F148 MSP430F147 MSP430F1491 MSP430F1481 MSP430F1471
MSP430F135 MSP430F133
Detailed Description
Copyright © 2000–2018, Texas Instruments Incorporated
6
Detailed Description
6.1
CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-
register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are
dedicated as program counter, stack pointer, status register, and constant generator, respectively. The
remaining registers are general-purpose registers (see Figure 6-1).
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word and
byte data.
Figure 6-1. CPU Registers



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