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MSP430F14X Datasheet(PDF) 51 Page - Texas Instruments |
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MSP430F14X Datasheet(HTML) 51 Page - Texas Instruments |
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51 / 83 page ![]() P2IN.5 P2OUT.5 Pad Logic P2DIR.5 P2SEL.5 Module X OUT Edge Select Interrupt P2SEL.5 P2IES.5 P2IFG.5 P2IE.5 P2IRQ.5 Direction Control P2.5/ROSC 0 1 0 1 Interrupt Flag Set EN Q DCOR Module X IN EN D to 0 1 DC Generator Bus Keeper CAPD.5 DCOR: Control bit from Basic Clock module. If it is set, P2.5 is disconnected from P2.5 pad. Internal to Basic Clock Module V CC 0: Input 1: Output From Module 51 MSP430F149, MSP430F148, MSP430F147 MSP430F1491, MSP430F1481, MSP430F1471 MSP430F135, MSP430F133 www.ti.com SLAS272H – JULY 2000 – REVISED MAY 2018 Submit Documentation Feedback Product Folder Links: MSP430F149 MSP430F148 MSP430F147 MSP430F1491 MSP430F1481 MSP430F1471 MSP430F135 MSP430F133 Detailed Description Copyright © 2000–2018, Texas Instruments Incorporated Figure 6-13. Port P2 (P2.5) Diagram Table 6-19. Port P2 (P2.5) Pin Functions PnSel.x PnDIR.x DIRECTION CONTROL FROM MODULE PnOUT.x MODULE X OUT PnIN.x MODULE X IN PnIE.x PnIFG.x PnIES.x P2Sel.5 P2DIR.5 P2DIR.5 P2OUT.5 DVSS P2IN.5 unused P2IE.5 P2IFG.5 P2IES.5 |
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