MSP430F14X datasheet(18/83 Pages) TI

18 / 83 page

MSP430F149, MSP430F148, MSP430F147

MSP430F1491, MSP430F1481, MSP430F1471

MSP430F135, MSP430F133

SLAS272H – JULY 2000 – REVISED MAY 2018

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Product Folder Links: MSP430F149 MSP430F148 MSP430F147 MSP430F1491 MSP430F1481 MSP430F1471

MSP430F135 MSP430F133

Specifications

(1)

For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

(2)

These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC (RθJC) value, which is based on a

JEDEC-defined 1S0P system) and will change based on environment and application. For more information, see these EIA/JEDEC

standards:

•

JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)

•

JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

•

JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages

•

JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements

(3)

N/A = not applicable

5.5

Thermal Resistance Characteristics

over recommended operating supply voltage and free-air temperature (unless otherwise noted)

THERMAL METRIC(1)

VALUE(2)

UNIT

64-PIN

PAG

64-PIN

RTD

RθJA

Junction-to-ambient thermal resistance, still air

52.0

52.7

25.0

°C/W

RθJC(TOP)

Junction-to-case (top) thermal resistance

14.4

11.2

14.2

°C/W

RθJB

Junction-to-board thermal resistance

23.0

23.4

9.6

°C/W

ΨJB

Junction-to-board thermal characterization parameter

22.7

23.1

9.5

°C/W

ΨJT

Junction-to-top thermal characterization parameter

0.6

0.3

0.2

°C/W

RθJC(BOTTOM)

Junction-to-case (bottom) thermal resistance

N/A(3)

1.3

°C/W

5.6

Schmitt-Trigger Inputs – Ports P1, P2, P3, P4, P5, and P6

over recommended operating supply voltage and free-air temperature (unless otherwise noted)

PARAMETER

VCC

MIN

MAX

UNIT

VIT+

Positive-going input threshold voltage

2.2 V

1.1

1.5

3 V

1.5

1.9

VIT–

Negative-going input threshold voltage

2.2 V

0.4

0.9

3 V

0.9

1.3

Vhys

Input voltage hysteresis (VIT+ – VIT–)

2.2 V

0.3

1.1

3 V

0.5

5.7

Standard Inputs – RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)

over recommended operating supply voltage and free-air temperature (unless otherwise noted)

PARAMETER

VCC

MIN

MAX

UNIT

VIL

Low-level input voltage

2 2 V, 3 V

VSS

VSS + 0.6

VIH

High-level input voltage

0.8 × VCC

VCC

(1)

The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with

trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in MCLK

cycles.

(2)

Seven Timer_B capture/compare registers in MSP430F14x and MSP430F14x devices, and three Timer_B capture/compare registers in

MSP430F13x devices.

5.8

Inputs – Px.y, TAx, TBx

over recommended operating supply voltage and free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

MAX

UNIT

t(int)

External interrupt timing

Port P1.x and P2.x, External trigger pulse

duration to set interrupt flag(1)

2.2 V, 3 V

1.5

cycle

2.2 V

3 V

t(cap)

Timer A or Timer B capture timing

TA0, TA1, TA2,

TB0, TB1, TB2, TB3, TB4, TB5, TB6(2)

2.2 V

3 V

f(TAext),

f(TBext)

Timer_A or Timer_B clock frequency

externally applied to pin

TACLK, TBCLK, INCLK: t(H)= t(L)

2.2 V

MHz

3 V

MSP430F14X Datasheet(PDF) 18 Page - Texas Instruments

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