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MSP430F14X Datasheet(PDF) 26 Page - Texas Instruments

Part # MSP430F14X
Description  MSP430F14x, MSP430F14x1, MSP430F13x Mixed-Signal Microcontrollers
PDF  83 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

MSP430F14X Datasheet(HTML) 26 Page - Texas Instruments

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MSP430F149, MSP430F148, MSP430F147
MSP430F1491, MSP430F1481, MSP430F1471
MSP430F135, MSP430F133
SLAS272H – JULY 2000 – REVISED MAY 2018
www.ti.com
Submit Documentation Feedback
Product Folder Links: MSP430F149 MSP430F148 MSP430F147 MSP430F1491 MSP430F1481 MSP430F1471
MSP430F135 MSP430F133
Specifications
Copyright © 2000–2018, Texas Instruments Incorporated
(1)
The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
(2)
Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
5.20 Crystal Oscillator, LFXT1
over recommended operating supply voltage and free-air temperature (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
CXIN
Integrated input capacitance
XTS = 0, LF oscillator selected
2.2 V, 3 V
12
pF
XTS = 1, XT1 oscillator selected
2
CXOUT
Integrated output capacitance
XTS = 0, LF oscillator selected
2.2 V, 3 V
12
pF
XTS = 1, XT1 oscillator selected
2
VIL
Low-level input voltage at XIN(2)
2.2 V, 3 V
VSS
0.2 × VCC
V
VIH
High-level input voltage at XIN(2)
2.2 V, 3 V
0.8 x VCC
VCC
V
(1)
The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
(2)
Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
5.21 Crystal Oscillator, XT2
over recommended operating supply voltage and free-air temperature (unless otherwise noted)
(1)
PARAMETER
VCC
MIN
TYP
MAX
UNIT
CXT2IN
Input capacitance
2.2 V, 3 V
2
pF
CXT2OUT
Output capacitance
2.2 V, 3 V
2
pF
VIL
Low-level input voltage at XT2IN(2)
2.2 V, 3 V
VSS
0.2 × VCC
V
VIH
High-level input voltage at XT2IN(2)
2.2 V, 3 V
0.8 x VCC
VCC
V
(1)
The signal applied to the USART0 USART1 receive terminal (URXD0 or URXD1) must meet the timing requirements of t(τ) to ensure
that the URXS flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum timing condition of t(τ). The operating
conditions to set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative
transitions on the URXD0 or URXD1 line.
5.22 USART0, USART1
over recommended operating supply voltage and free-air temperature (unless otherwise noted)
PARAMETER
VCC
MIN
TYP
MAX
UNIT
t(τ)
USART0 or USART1 deglitch time(1)
2.2 V
200
430
800
ns
3 V
150
280
500



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