DSP56374UMSLASHD datasheet(14/64 Pages) FREESCALE

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DSP56374 Data Sheet, Rev. 4.2

Signal Groupings

Freescale Semiconductor

SCKR

Input or output

GPIO

disconnected

Receiver Serial Clock—SCKR provides the receiver serial

bit clock for the ESAI. The SCKR operates as a clock input

or output used by all the enabled receivers in the

asynchronous mode (SYN=0), or as serial flag 0 pin in the

synchronous mode (SYN=1).

When this pin is configured as serial flag pin, its direction is

determined by the RCKD bit in the RCCR register. When

configured as the output flag OF0, this pin will reflect the

value of the OF0 bit in the SAICR register, and the data in

the OF0 bit will show up at the pin synchronized to the

frame sync in normal mode or the slot in network mode.

When configured as the input flag IF0, the data value at the

pin will be stored in the IF0 bit in the SAISR register,

synchronized by the frame sync in normal mode or the slot

in network mode.

PC0

Input, output, or

disconnected

Port C0—When the ESAI is configured as GPIO, this signal

is individually programmable as input, output, or internally

disconnected.

The default state after reset is GPIO disconnected.

Internal Pull down resistor.

This input is 5 V tolerant.

SCKT

Input or output

GPIO

disconnected

Transmitter Serial Clock—This signal provides the serial bit

rate clock for the ESAI. SCKT is a clock input or output used

by all enabled transmitters and receivers in synchronous

mode, or by all enabled transmitters in asynchronous

mode.

PC3

Input, output, or

disconnected

Port C3—When the ESAI is configured as GPIO, this signal

is individually programmable as input, output, or internally

disconnected.

The default state after reset is GPIO disconnected.

Internal Pull down resistor.

This input is 5 V tolerant.

Table 10. Enhanced Serial Audio Interface Signals (continued)

Signal Name

Signal Type

State during

Reset

Signal Description

DSP56374UM/D Datasheet(PDF) 14 Page - Freescale Semiconductor, Inc

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