TDA8006HSLASHC2 datasheet(12/40 Pages) PHILIPS

12 / 40 page

2000 Feb 21

Philips Semiconductors

Product speciﬁcation

Multiprotocol IC Card coupler

TDA8006

ISO 7816 security

The correct sequence during activation and deactivation of

the card is ensured by a specific sequencer clocked at a

frequency which is a division ratio of the internal oscillator.

Activation (bit CMDVCC within the ports extension register

HIGH) is only possible if the card is present (pin PRES

HIGH or LOW according to the mask option) and if the

supply voltage is correct (ALARM signal inactive).

The presence of the card is signalled to the controller by

the OFF bit (within the UART status register), generating

an interrupt, if enabled, when toggling.

During a session, the sequencer performs an automatic

emergency deactivation in the event of card take-off,

supply voltage drop or short circuit. The OFF bit goes

LOW, thereby warning the controller through the interrupt

line INT0 and the status register.

Peripheral interface (see Figs 5 and 6)

This block allows parallel communication with the four

peripherals (ISO 7816 UART, clock generator, on/off

sequencer and auxiliary RAM) through an 8-bit data bus,

6-bit address and control bus and one interrupt line to the

controller. The data bus consists of ports P40 (data bit 0)

to P47 (data bit 7). The address bus consists of ports AD0

(P12), AD1 (P13), AD2 (P14) and AD3 (P15). The control

lines are R/W (P16) and EN (P17). The interrupt line is

INT0.

During a read operation, EN goes LOW allowing the

controller to read data on the bus. During a write operation,

the data should be present on the bus before asserting EN

LOW which allows the data to be written to the registers.

After resetting EN HIGH, the controller must release the

bus by setting port P4 HIGH again (the transition times on

port P4 are less than 500 ns).

The interrupt line is reset HIGH when reading out the

status register.

READ OPERATION

• Set port P4 to FFH

• Select the register with AD0, AD1, AD2, AD3

• Assert R/W HIGH

• Assert EN LOW; the data is available on data bus P4

• Read the data on port P4

• Set EN HIGH; the bus is set to high impedance.

WRITE OPERATION

• Select the correct register with AD0, AD1, AD2, AD3

• Assert R/W LOW

• Write data to the data bus port P4

• Assert EN LOW; the data is written to the register

• Set EN HIGH

• Set port P4 to FFH; the bus is set to high impedance.

Integrated precharges allow fast rising edges on port P4

when changing from read mode to write mode, thus

avoiding the need to trigger the active pull-ups on port P4.

handbook, full pagewidth

MGR229

DATA

R/W

AD0 to AD3

read data cycle

write data cycle

DATA

Fig.5 Use of peripheral interface.

TDA8006H/C2 Datasheet(PDF) 12 Page - NXP Semiconductors

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