TDA8006HSLASHC2 datasheet(17/40 Pages) PHILIPS

17 / 40 page

2000 Feb 21

Philips Semiconductors

Product speciﬁcation

Multiprotocol IC Card coupler

TDA8006

On/off controller

Table 8

On/off controller bits (PER; address 7; write only; all bits cleared after reset)

BIT

NAME

DESCRIPTION

CMDVCC; set and reset by software

set to 1 for starting activation sequence of the card, and reset

to 0 for starting deactivation

RSTIN; set and reset by software

control line RST for card contact C2 in manual mode (active

HIGH)

Force Inverse Parity (FIP); set and reset by

software

when LOW, the UART processes the parity according to

ISO 7816; when HIGH, the UART processes the inverse parity

(which causes parity errors during transmission and ‘not

acknowledge’ signals during reception)

automatic ATR processing enabling

(ATREN); set by software, reset by

hardware

when HIGH, the UART automatically counts the clock pulses

during ATR and controls the RST contact; this bit is

automatically reset by hardware when a start bit is detected

on I/O or when the card is declared as mute; when LOW, this

automatic processing is disabled (manual mode)

K0; set and reset by software

auxiliary

±2 mA push-pull output control (inverted output)

K1; set and reset by software

auxiliary

±2 mA push-pull output control (inverted output)

K2; set and reset by software

auxiliary

±2 mA push-pull output control (inverted output)

K3; set and reset by software

auxiliary

±2 mA push-pull output control (inverted output)

The on/off controller is used for activating or deactivating

the card, for controlling contact C2 (RST) manually

through RSTIN or automatically, for forcing inverse parity

(for flow control or test purposes), and for controlling four

independent push-pull output lines K0 to K3.

After having cleared the ISO 7816 UART reset bit (see

UART configuration register) and checking the card

presence within the status register, the software may

initiate an activation sequence by setting bit CMDVCC

HIGH. It may also initiate a deactivation sequence by

resetting this bit (see activation and deactivation

sequences).

The timings during the ATR may be checked either

manually (using RSTIN and t3/t5 for counting clock pulses)

or automatically by setting bit ATREN HIGH (see Section

“Activation sequence”). In this case, hardware controls

both RST and the counting of CLK pulses. Bit ATREN is

reset by hardware when a start bit has been detected

before 2

× 40100 CLK pulses for versions C2 and C3

× 45000 CLK pulses for version C1), or when the card

is declared as ‘mute’. Setting this bit HIGH again during a

session initiates a warm reset.

A warm reset may also be done manually by using RSTIN

and t3/t5 again.

ISO 7816 UART

The ISO 7816 UART handles all specific requirements

defined in ISO 7816 T = 0 and T = 1 protocol types. It is

also able to deal with synchronous cards (in conjunction

with contacts C4 and C8). In addition, there is a possibility

to force parity errors for test purposes or flow control.

The counting of CLK cycles during ATR is possible by

either hardware or software.

The ISO 7816 UART is configured with 2 registers: UART

Configuration Register (UCR) and Guard Time Register

(GTR).

When timings are given in terms of ETU (Elementary Time

Unit as defined by ISO 7816), then the reference is the

negative edge of the start bit of the character being

received or transmitted, unless otherwise specified.

TDA8006H/C2 Datasheet(PDF) 17 Page - NXP Semiconductors

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