MFS2301BMBACEP datasheet(23/230 Pages) NXP

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NXP Semiconductors

FS23

Safety system basis chip (SBC) with power management, CAN FD and LIN transceivers

12.3 Main state machine description

Power-on reset and power-up sequence

The FS23 starts when VBOS > VBOS_POR and VDIG > VDIG_POR. VBOS is the first supply to start. The internal

1.6 V supply of the digital circuitry, VDIG, is generated from VBOS. When VBOS > VBOS_UV, the high-power

(HP) analog circuitry is enabled and the OTP registers content is loaded into mirror registers. When VSUP >

VSUP_UV , the power-up sequence starts in Slot 0, with at least V1 regulator. The remaining regulators start

according to the power-up sequencing configured by OTP.

Transition to fail-safe during the power up

During the power-up sequence, if VBOS < VBOS_UV, the device goes to Fail-safe mode and all regulators are

disabled. If an overvoltage or an overtemperature is detected, the device goes to fail-safe, depending on the

OTP configuration.

Normal mode

When the power up is finished, the main state machine is in Normal mode, which is the application running

mode. If VSUP < VSUP_UV, an interrupt is generated but it has no effect on the state machine. If VBOS <

VBOS_UV, the device goes to Fail-safe mode.

Transitions to low-power modes

The device can go to Low-power modes via an SPI/I2C command from the MCU. A GO2LPOFF command will

start the power-down sequence to go in LPOFF mode, and a GO2LPON command will start the power-down

sequence to go in LPON mode. The device goes into Low-power mode after the power-down sequence to stop

all the regulators in the reverse order of the power-up sequence. In case the device goes in LPON, V1 regulator

is not shut down and is kept ON.

Transition to Fail-safe from Normal mode

In case of loss of VBOS (VBOS < VBOS_UV), the device goes directly to Fail-safe mode without power-down

sequence.

In case of overvoltage detection, or TSD detection on a regulator, depending on OTP configuration, or when

the fault error counter reaches its maximum value, the device stops and goes directly to Fail-safe mode without

power-down sequence.

Fail-safe state exit

Three behaviors are configurable by OTP to exit the Fail-safe state:

• Automatic restart after TFS_DUR (autoretry feature, configurable by OTP at 100 ms or 4 s)

• Semi-automatic restart after TFS_DUR, the device exits Fail-safe state and enters LPOFF states, then waits for

a wake-up source to transition to M2 and restart (FS_LPOFF = 1 and KEY_OFFON_EN_OTP = 0).

• Restart on Key OFF – Key ON event: Key OFF – Key ON feature is meant to be used when the ignition

signal is connected to WAKE1. When enabled, the car driver must turn OFF then ON the ignition signal

to restart the device from fail-safe. In this case, the device will only exit fail-safe when WAKE1 = 0 and

KEY_OFFON_EN_OTP = 1, and will transition to LPOFF. There, the device will wait for a wake-up event (that

is, WAKE1 = 1) to transition to M2 and restart.

• This feature requires WAKE1 to be configured as a direct wake-up source.

Waking up from Low-power modes

When waking up from Low-power modes, it is possible to reduce the startup time by bypassing the M3 state

(OTP content loaded in the mirror register) using LOAD_OTP_BYP SPI/I²C bit. This is also valid when exiting

fail-safe.

When waking up from LPON only, it is possible to bypass slots 1 and 2 if all of the regulators are configured to

start in Slot 0. This can be configured by OTP (SLOT_BYP_OTP) or later by SPI/I²C (SLOT_BYP).

FS23

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 7.0 — 16 October 2024

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