R5F526TACDFM datasheet(5/142 Pages) RENESAS

5 / 142 page

R01DS0407EJ0120 Rev.1.20

Page 5 of 142

Oct 31, 2024

RX26T Group

1. Overview

Timers

Compare match timer W

(CMTW)

 (32 bits × 1 channel) × 2 units

 Compare-match, input-capture input, and output-comparison output are available.

 Select from among four internal clock signals (PCLKB/8, PCLKB/32, PCLKB/128,

PCLKB/512)

Interrupt requests can be output in response to compare-match, input-capture, and

output-comparison events.

Watchdog timer (WDTA)

 14 bits × 1 channel

 Select from among 6 counter-input clock signals (PCLKB/4, PCLKB/64, PCLKB/128,

PCLKB/512, PCLKB/2048, PCLKB/8192)

Independent watchdog

timer (IWDTa)

 14 bits × 1 channel

 Counter-input clock: IWDT-dedicated on-chip oscillator

 Dedicated clock/1, dedicated clock/16, dedicated clock/32, dedicated clock/64, dedicated

clock/128, dedicated clock/256

 Window function: The positions where the window starts and ends are specifiable (the

window defines the timing with which refreshing is enabled and disabled).

 Event linking by the ELC

Multifunction timer pulse

unit 3 (MTU3d)

 9 channels (16 bits × 9 channels)

 Maximum of 28 pulse-input/output and 3 pulse-input possible

 Select from among 14 counter-input clock signals for each channel (PCLKC/1, PCLKC/2,

PCLKC/4, PCLKC/8, PCLKC/16, PCLKC/32, PCLKC/64, PCLKC/256, PCLKC/1024,

MTCLKA, MTCLKB, MTCLKC, MTCLKD, MTIOC1A)

11 of the signals are available for channels 1, 3, 4, 12 are available for channel 2, and 10

are available for channel 5.

 43 output compare/input capture registers

 Counter clear operation (synchronous clearing by compare match/input capture)

 Simultaneous writing to multiple timer counters (TCNT)

 Simultaneous register input/output by synchronous counter operation

 Buffered operation

 Support for cascade-connected operation

 45 interrupt sources

 Automatic transfer of register data

 Pulse output mode

Toggle/PWM/complementary PWM/reset-synchronized PWM

 Complementary PWM output mode

Outputs non-overlapping waveforms for controlling 3-phase inverters

Automatic specification of dead times

PWM duty cycle: Selectable as any value from 0% to 100%

Delay can be applied to requests for A/D conversion.

Non-generation of interrupt requests at peak or trough values of counters can be

selected.

Double buffer configuration

 Reset synchronous PWM mode

Three phases of positive and negative PWM waveforms can be output with desired duty

cycles.

 Phase-counting mode: 16-bit mode (channels 1 and 2); 32-bit mode (channels 1 and 2)

 Counter functionality for dead-time compensation

 Generation of triggers for A/D converter conversion

The timing of the generation of requests to start A/D conversion can be monitored by an

external pin.

 A/D conversion start triggers can be skipped

 Digital filter function for signals on the input capture and external counter clock pins

 Event linking by the ELC

 Internal peripheral bus clock: PCLKA

 Counter reference clock: PCLKC

 Frequency ratio: PCLKA to PCLKC = 1: N (N = 1 or 2)

Port output enable 3

(POE3D)

 Control of the high-impedance state of the MTU/GPTW’s waveform output pins, and

control of switching to the general I/O port pin

 7 pins for input from signal sources: POE0, POE4, POE8, POE9, POE10, POE11,

POE12

 Initiation by detection of short-circuited outputs (detection of PWM outputs that have

become an active level simultaneously)

 Initiation by comparator detection/oscillation stop detection/software

 Additional programming of output control target pins is enabled

Table 1.1

Outline of Specifications (4/9)

Classification

Module/Function

Description

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