R5F526TACDFM datasheet(94/142 Pages) RENESAS

94 / 142 page

R01DS0407EJ0120 Rev.1.20

Page 94 of 142

Oct 31, 2024

RX26T Group

2. Electrical Characteristics

2.4.5.10

RSCI

Note 1. tPcyc refers to the period of PCLKB in RSCI8 and RSCI9, and of PCLKA in RSCI11.

Figure 2.44

SCK Clock Input Timing

Table 2.34

RSCI Timing

Conditions: VCC = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5 V,

VSS = AVSS0 = AVSS1 = AVSS2 = 0 V, Ta = Topr,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-drive output is selected by the driving ability control register.

Item

Symbol

Min.

Max.

Unit*1

Test Conditions

RSCI

Input clock cycle

Asynchronous

tScyc

—

tPcyc

Figure 2.44

Clock

synchronous

2—

Input clock pulse width

tSCKW

0.4

0.6

tScyc

Input clock rise time

tSCKr

—5

Input clock fall time

tSCKf

—5

Output clock cycle

Asynchronous

tScyc

6—

tPcyc

Clock

synchronous

2—

Output clock pulse width

tSCKW

0.4

0.6

tScyc

Output clock rise time

tSCKr

—5

Output clock fall time

tSCKf

—5

Receive data setup time

Master

tRXS

–1.5

—

VCC ≥ 4.5 V

Figure 2.45

3.5

—

VCC < 4.5 V

Slave

2.5

—

Figure 2.45

Receive data hold time

Master

tRXH

—

Slave

2.5

—

Transmit data delay time

Master

tTXD

—4

Slave

—

VCC ≥ 4.5 V

Figure 2.45

—

VCC < 4.5 V

tSCKW

tSCKr

tSCKf

tScyc

SCKn

(n = 008, 009, and 011)

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