R5F526TACDFM datasheet(80/142 Pages) RENESAS

80 / 142 page

R01DS0407EJ0120 Rev.1.20

Page 80 of 142

Oct 31, 2024

RX26T Group

2. Electrical Characteristics

2.4.5

Timing of On-Chip Peripheral Modules

2.4.5.1

I/O Port

Note 1. tPBcyc: PCLKB cycle

Figure 2.14

I/O Port Input Timing

2.4.5.2

TMR

Note 1. tPBcyc: PCLKB cycle

Figure 2.15

TMR Clock Input Timing

Table 2.23

I/O Port Timing

Conditions: VCC = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5 V,

VSS = AVSS0 = AVSS1 = AVSS2 = 0 V, Ta = Topr,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-drive output is selected by the driving ability control register.

Item

Symbol

Min.

Max.

Unit*1

Test

Conditions

I/O ports

Input data pulse width

tPRW

1.5

—

tPBcyc

Figure 2.14

Table 2.24

TMR Timing

Conditions: VCC = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5 V,

VSS = AVSS0 = AVSS1 = AVSS2 = 0 V, Ta = Topr,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-drive output is selected by the driving ability control register.

Item

Symbol

Min.

Max.

Unit*1

Test

Conditions

TMR

Timer clock pulse width

Single-edge

setting

tTMCWH,

tTMCWL

1.5

—

tPBcyc

Figure 2.15

Both-edge

setting

2.5

—

Port

PCLKB

tPRW

PCLKB

TMCI0 to TMCI7

tTMCWL

tTMCWH

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