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R5F526TACDFM Datasheet(PDF) 1 Page - Renesas Technology Corp |
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R5F526TACDFM Datasheet(HTML) 1 Page - Renesas Technology Corp |
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1 / 142 page  RX26T Group Renesas MCUs Datasheet R01DS0407EJ0120 Rev.1.20 Page 1 of 142 Oct 31, 2024 Features ■ 32-bit RXv3 CPU core Maximum operating frequency: 120 MHz Capable of 709 CoreMark in operation at 120 MHz A collective register bank save function is available. Supports the memory protection unit (MPU) JTAG and FINE (one-line) debugging interfaces ■ Low-power design and architecture Operation from a single 2.7- to 5.5-V supply Three low-power modes ■ On-chip code flash memory Supports versions with up to 512 Kbytes of ROM Operation at 120 MHz (with no waiting) User code is programmable by on-board or off-board programming. Programming/erasing as background operations (BGOs) A dual-bank structure allows exchanging the start-up bank. ■ On-chip data flash memory 16 Kbytes, reprogrammable up to 100,000 times Programming/erasing as background operations (BGOs) ■ On-chip SRAM 64 K/48Kbytes of SRAM (with no waiting) ■ Data transfer DMACAa: 8 channels DTCb: 1 channel ■ ELC Module operation can be initiated by event signals without using interrupts Linked operation between modules is possible when the CPU is in sleep mode ■ Reset and supply management Power-on reset (POR) Low voltage detection (LVD) with voltage settings ■ Clock functions The main clock oscillator is connectable to an 8- to 24-MHz external crystal resonator and usable as the PLL reference clock. Internal 240-kHz LOCO and HOCO selectable from 16, 18, and 20 MHz 120-kHz clock for the IWDTa ■ Independent watchdog timer 120-kHz IWDT-dedicated on-chip oscillator clock operation ■ Useful functions for IEC60730 compliance Oscillation-stoppage detection, functions for self-diagnosis and detection of disconnection for the A/D converter, clock frequency accuracy measurement circuit, independent watchdog timer, RAM test-assisting function by DOC, and CRCA, etc. Register write protection function can protect values in important registers against overwriting. ■ Encryption functions (Trusted Secure IP Lite) 128- or 256-bit key length of AES for ECB, CBC, GCM, others True random number generator Unauthorized access to the encryption engine is disabled and imposture and falsification of information are prevented Safe management of keys ■ Up to 83 pins for general I/O ports 5-V tolerance, open drain, input pull-up, switchable driving ability, and retention of the port output ■ Various communications interfaces CAN FD: Compliant with ISO11898-1:2015, standard frame and extended frame (1 channel) SCIk and SCIh with multiple functionalities (up to 4 channels) Choose from among asynchronous mode, clock-synchronous mode, smart-card interface mode, simplified SPI, simplified I2C, and extended serial mode. Up to three RSCIs with Manchester encoding and HBS functionality I2C bus interface (RIICa) for transfer at up to 400 kbps (fast mode), capable of SMBus operation (1 channel) I3C bus interface (RI3C) for the single data rate (SDR) mode (1 channel) RSPId (1 channel) for transfer at up to 30 Mbps ■ Up to 29 extended-function timers 32-bit (products with 64 Kbytes of RAM) or 16-bit (products with 48 Kbytes of RAM) GPTWa (8 channels): operation at 120 MHz, input capture, output compare, PWM waveforms: 10 output channels in single-phase complementary PWM mode/3 output channels in 3- phase complementary PWM mode/2 output channels in 5-phase complementary PWM mode, phase-counting mode, linkage with comparator (counting operation, PWM negate control) 16-bit MTU3d (9 channels): operation at 120 MHz, input capture, output compare, PWM waveforms: 2 output channels in 3-phase complementary PWM mode, phase-counting mode 8-bit TMRb (8 channels) 16-bit CMT (4 channels) ■ High-resolution PWM waveform generation circuit (HRPWM): 4 channels Controlling the timing of rising or falling of the PWM output waveform for 32-bit GPTWa is realized with minimum of 260 ps resolution (in operation at 120 MHz) ■ 12-bit A/D converter (S12ADH) Products with 64 Kbytes of RAM Three 12-bit units of sample-and-hold circuit included: Unit 0 (4 channels for 3 sample-and-hold circuits), Unit 1 (4 channels for 3 sample-and-hold circuits), Unit 2 (14 channels) Products with 48 Kbytes of RAM Two 12-bit units of sample-and-hold circuit included: Unit 0 (7 channels for 3 sample-and-hold circuits), Unit 2 (8 channels) ■ Analog Comparator (CMPCa): 6 channels ■ 12-bit D/A converter: 2 channels Usable as a reference voltage for the analog comparator ■ Temperature sensor for measuring temperature within the chip ■ Recommended operating temp. range (Topr) D-version: –40C to +85C G-version: –40C to +105C PLQP0100KB-B 14 × 14 mm, 0.5 mm pitch PLQP0080KB-B 12 × 12 mm, 0.5 mm pitch PLQP0064KB-C 10 × 10 mm, 0.5 mm pitch PLQP0048KB-B 7 × 7 mm, 0.5 mm pitch PWQN0064KF-A 9 × 9 mm, 0.5 mm pitch PWQN0048KC-A 7 × 7 mm, 0.5 mm pitch PWQN0032KE-A 5 × 5 mm, 0.5 mm pitch 120-MHz, 32-bit RX MCU, on-chip FPU, 709 CoreMark, Supportive of 5V power supply, up to 512-KB flash memory, up to 64-KB SRAM, 16-KB data flash memory, various communications interfaces including CAN FD, Simultaneous sampling with 3 units of 12-bit A/D converter (up to 7 channels), Analog comparator (6 channels), 120 MHz PWM (4 channels for 3-phase complementary, 2 channels for 5-phase complementary, 10 channels for single-phase complementary), 4-channel high-resolution PWM with resolution of 260 ps at the minimum, Encryption functions R01DS0407EJ0120 Rev.1.20 Oct 31, 2024 Features |
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