R5F526TACDFM datasheet(81/142 Pages) RENESAS

81 / 142 page

R01DS0407EJ0120 Rev.1.20

Page 81 of 142

Oct 31, 2024

RX26T Group

2. Electrical Characteristics

2.4.5.3

MTU

Note 1. tPCcyc: PCLKC cycle

Figure 2.16

MTU Input Capture Input Timing

Figure 2.17

MTU Clock Input Timing

Table 2.25

MTU Timing

Conditions: VCC = 2.7 to 5.5 V, AVCC0 = AVCC1 = AVCC2 = 3.0 to 5.5 V,

VSS = AVSS0 = AVSS1 = AVSS2 = 0 V, Ta = Topr,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz,

Output load conditions: VOH = 0.5 × VCC, VOL = 0.5 × VCC, C = 30 pF,

High-drive output is selected by the driving ability control register.

Item

Symbol

Min.

Max.

Unit*1

Test

Conditions

MTU

Input capture input pulse

width

Single-edge

setting

tMTICW

1.5

—

tPCcyc

Figure 2.16

Both-edge

setting

2.5

—

Timer clock pulse width

Single-edge

setting

tMTCKWH,

tMTCKWL

1.5

—

tPCcyc

Figure 2.17

Both-edge

setting

2.5

—

Phase counting

mode

2.5

—

Input capture

input

PCLKC

tMTICW

MTCLKA to

MTCLKD,

MTIOC1A

PCLKC

tMTCKWL

tMTCKWH

R5F526TACDFM Datasheet(PDF) 81 Page - Renesas Technology Corp

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