R5F526TACDFM datasheet(112/142 Pages) RENESAS

112 / 142 page

R01DS0407EJ0120 Rev.1.20

Page 112 of 142

Oct 31, 2024

RX26T Group

2. Electrical Characteristics

2.4.5.14

RI3C

Note 1. This is approximately equal to tLOWmin + tDS_ODmin + trDA_ODtyp + tSU_ODmin.

Note 2. The controller may use a shorter low period if it knows that this is safe, i.e., that SDA is already above VIH.

Note 3. On a legacy bus where I2C devices need to see start, the tCAS Min value is further constrained.

Note 4. Targets that do not support the optional ENTASx CCCs shall use the tCAS Max value shown for ENTAS3

Note 5. On a mixed bus with Fm legacy I2C devices, tAVAL is 300 ns shorter than the Fm bus free condition time (tBUF)

Figure 2.68

RI3C Start Condition Timing

Table 2.40

RI3C Timing (Open Drain Timing Parameters)

Conditions: VCC = AVCC0 = AVCC1 = AVCC2 = 3.0 to 3.6 V,

VSS = AVSS0 = AVSS1 = AVSS2 = 0 V, Ta = Topr,

PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz

Item

Symbol

Min.

Typ.

Max.

Unit

Test

Conditions

SCL clock low period

tLOW_OD

200*1, *2

—

Figure 2.68

tDIG_OD_L

tLOW_ODmin +

tfDA_ODmin

——

SDA signal fall time

tfDA_OD

tCF

—

Figure 2.68

SDA data setup time open drain mode

tSU_OD

3*1

—

Figure 2.68,

Figure 2.69

Clock after START (S) condition

tCAS

38.4 ns*3

—

For ENTAS0: 1 µs

—

Figure 2.68

—

For ENTAS1: 100 µs

—

For ENTAS2: 2 ms

—

For ENTAS3: 50 ms*4

Clock before STOP (P) condition

tCBP

tCASmin/2

—

sec

Figure 2.70

Current controller to secondary controller

overlap time during handoff

tCRHPOverlap

tDIG_OD_Lmin

—

Figure 2.71

Bus available condition

tAVAL

1*5

——

µs

Bus idle condition

tIDLE

1—

—

Time internal where new controller not

driving SDA low

tNEWCRLock

tAVALmin

—

µs

Figure 2.71

SDA

SCL

0.7 × VCC

0.3 × VCC

0.7 × VCC

0.3 × VCC

tf DA_OD

tDS_OD

tSU_OD

tr DA_OD

tCAS

tCF

tLOW_OD

tCR

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