PSD511B1 datasheet(78/153 Pages) STMICROELECTRONICS

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PSD5XX Family

9.6.1.5 Time Capture Mode

In the time capture mode, the Counter/Timer is capable of measuring the time

(by counting clock pulses) between events. Figure 39 shows the CTU configuration for

time capture. All the Counter/Timer registers must be cleared during initialization of the

Time Capture mode. Here the Counter is enabled to count via software only. The CTUs

continuously count. A Load/Store pulse triggers the storing of the Counter’s contents into

the associated image register. The image register effectively contains a “snap shot” of the

Counter at the time of the pulse. The CTU Store input is edge-triggered by events, the

events being:

t Pin Driven.

t PPLD Macrocell Driven.

t Software Driven.

A Freeze signal is used to ensure that image data is stable during Microcontroller reads

which is similar to the description of event Counter Microcontroller read accesses. Two

CTUs in time capture mode can be used to capture the rising and the falling edges of a

pulse, the difference of the measurements being the pulse width. The counter continues to

count regardless of the Freeze Acknowledge state.

Note that the time span between two consecutive edges of Time Capture must be greater

than one timer clock cycle in order to be captured.

9.6.1.6 WatchDog Counter/Timer

Counter/Timer-2 can be operated as a WatchDog Timer in both Waveform/Pulse and Event

count/time capture modes. In Event count/time capture mode, Counter/Timer-2 can be

configured only as WatchDog. Figure 40 shows the control signals of the CTU when in

WatchDog mode. When the WatchDog mode is active, CTU2 counts down and at the

terminal count of Counter-2 a WatchDog condition occurs. To avoid the WatchDog from

occurring, a "Write" to the Software Load/Store Bit-2 in the "Software Load/Store Register"

has to take place before the Counter-2 underflows. This action reloads the Counter-2 with

the initial count value in the Image Register-2. Note that this initial count value cannot be

changed after the WatchDog mode is enabled.

The Terminal Count signal of a WatchDog could result in a pulse width that is equal to the

count value loaded into the Image Register of Counter/Timer-2. The active high WatchDog

pulse from Counter 2 is routed through the PPLD, enabling the user to inverse its polarity or

implement any other logic before driving the WatchDog output on a user defined I/O pin.

This signal could be used to drive a RESET pin or trigger a Non-Maskable interrupt on a

processor. Once Counter/Timer-2 is set to the WatchDog mode, it cannot be reconfigured

by software and it can get out of the WatchDog mode only by a RESET.

When the WatchDog is enabled in Power Down and Sleep modes, it remains active

regardless of the state of bit 7 (TMR CLK) in Power Management Mode Register PMMR0.

The WatchDog mode is enabled by setting the WatchDog bit in the global command

configured in pulse mode. In this case, bit 0 of the command register for CTU2 is set to “1”.

Counter/Timer

Operation

(Cont.)

PSD511B1 Datasheet(PDF) 78 Page - STMicroelectronics

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